Dynamic analog content addressable memory
A dynamic analog content addressable memory (CAM) cell uses volatile memory to store a range. The dynamic analog CAM cell includes an upper bound circuit and a lower bound circuit. The upper bound circuit includes a first pull-down transistor and a first controlled current generator. The first controlled current generator is configured to store an upper bound of the range in a first dynamic memory circuit, and to activate the first pull-down transistor when an analog input value is greater than the upper bound of the range. The lower bound circuit includes a second pull-down transistor and a second controlled current generator. The second controlled current generator is configured to store a lower bound of the range in a second dynamic memory circuit, and to activate the second pull-down transistor when the analog input value is less than the lower bound of the range.
1 . A device comprising:
a first dynamic memory circuit;
a first control transistor, the first control transistor and the first dynamic memory circuit being connected in series between a word line and a reference node;
a first pull-down transistor connected between a match line and the reference node, a gate of the first pull-down transistor connected to the first control transistor and the first dynamic memory circuit;
a second dynamic memory circuit;
a second control transistor, the second control transistor and the second dynamic memory circuit being connected in series between the word line and the reference node; and
a second pull-down transistor connected between the match line and the reference node, a gate of the second pull-down transistor connected to the second control transistor and the second dynamic memory circuit.
2 . The device of claim 1 , wherein the first dynamic memory circuit comprises a first weight capacitor and a first readout transistor, and the second dynamic memory circuit comprises a second weight capacitor and a second readout transistor.
3 . The device of claim 2 , wherein the first readout transistor and the first control transistor are part of a first voltage divider, and the second readout transistor and the second control transistor are part of a second voltage divider.
4 . The device of claim 2 , wherein the first control transistor is connected between the word line and the first readout transistor, the first readout transistor is connected between the first control transistor and the reference node, the second readout transistor is connected between the word line and the second control transistor, and the second control transistor is connected between the second readout transistor and the reference node.
5 . The device of claim 2 , wherein the first weight capacitor is connected between the reference node and a gate of the first readout transistor, and the second weight capacitor is connected between the reference node and a gate of the second readout transistor.
6 . The device of claim 1 , wherein the first control transistor is an n-type transistor and the second control transistor is an n-type transistor.
7 . The device of claim 1 , wherein a gate of the first control transistor and a gate of the second control transistor are connected to a source line.
8 . The device of claim 7 , further comprising:
a sensing circuit connected to the match line; and
a search/write circuit connected to the source line.
9 . The device of claim 1 , further comprising:
a first charging circuit connected to the first dynamic memory circuit; and
a second charging circuit connected to the second dynamic memory circuit.