Content-addressable memory (CAM) cell with P and N pass gates to same write bit line
A Content-Addressable Memory (CAM) cell has a latch of cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing. A node in the latch is applied to a gate of a data transistor in series with a select transistor to discharge a match line when select and latch data mismatch. Second data and select transistors receive inverse data from the latch for a CAM but receive data from a second cell latch for a Ternary Content-Addressable Memory (TCAM) cell with two latches per pair of select lines. When mismatches occur, even cells discharge the match line using n-channel data and select transistors while odd cells charge a complement match line using p-channel data and select transistors. The total number of p-channel and n-channel transistors in the cell can be equal when using complementary match lines.
1 . A Content-Addressable Memory (CAM) cell comprising:
a first pull-up transistor and a first pull-down transistor connected in series between a power supply and a ground, the first pull-up transistor and the first pull-down transistor connected at a first latch node;
a second pull-up transistor and a second pull-down transistor connected in series between the power supply and the ground, the second pull-up transistor and the second pull-down transistor connected at a second latch node;
wherein gates of the first pull-up transistor and of the first pull-down transistor are driven by the second latch node between the second pull-up transistor and the second pull-down transistor;
wherein gates of the second pull-up transistor and of the second pull-down transistor are driven by the first latch node between the first pull-up transistor and the first pull-down transistor;
a first n-channel pass transistor connected between the first latch node and a first bit line, and having a gate connected to a word line;
a second n-channel pass transistor connected between the second latch node and a second bit line, and having a gate connected to the word line;
a first p-channel pass transistor connected between the first latch node and the first bit line, and having a gate connected to an inverse word line;
a second p-channel pass transistor connected between the second latch node and the second bit line, and having a gate connected to the inverse word line;
a first data transistor with a gate connected to the second latch node, and a channel that conducts current controlled by the gate to a first connecting node; and
a first select transistor having a gate connected to a first select line and a channel connected between the first connecting node and a match line;
wherein the match line is perpendicular to the first select line, wherein the match line connects to other CAM cells in a row and the first select line connects to other CAM cells in a column of an array of the CAM cells arrayed into rows and columns,
a second data transistor with a gate connected to the first latch node, and a channel that conducts current controlled by the gate to a second connecting node; and
a second select transistor having a gate connected to a second select line and a channel connected between the second connecting node and the match line;
wherein a compare operation is performed by applying a compare bit from compare data to the second select line, and by applying an inverse of the compare bit to the first select line; wherein when the compare bit mismatches data stored in the CAM cell the match line is discharged through the first select transistor and the first data transistor, or is discharged through the second select transistor and the second data transistor,
wherein for cells in even columns;
the first data transistor and the second data transistor each further comprises an n-channel transistor having a source connected to the ground;
the first select transistor and the second select transistor each further comprises an n-channel transistor;
the match line further comprises a true match line that is precharged high before the compare operation and is discharged low when a mismatch occurs in an even column;
wherein for cells in odd columns;
the first data transistor comprises a p-channel transistor with a source connected to the power supply;
the second data transistor comprises a p-channel transistor with a source connected to the power supply;
the first select transistor and the second select transistor each comprise a p-channel transistor;
the match line is a complement match line that is precharged low before the compare operation and is discharged high when a mismatch occurs in an odd column;
further comprising, for a row of the CAM cell;
a true precharge transistor that precharges the true match line high before the compare operation;
a complement precharge transistor that precharges the complement match line low before the compare operation; and
match logic that signals a match for the row of the CAM cell when the true match line remains high and the complement match line remains low during the compare operation,
wherein a total number of n-channel transistors equals a total number of p-channel transistors in a pair of the CAM cell, the pair including a CAM cell in the even columns and a CAM cell in the odd columns,
whereby the CAM cell is P/N balanced over a pair of odd and even columns.
2 . The CAM cell of claim 1 wherein the power supply further comprises a logic power supply that is used to power logic gates external to the CAM cell.
3 . A Content-Addressable Memory (CAM) cell comprising:
a first pull-up transistor and a first pull-down transistor connected in series between a power supply and a ground, the first pull-up transistor and the first pull-down transistor connected at a first latch node;
a second pull-up transistor and a second pull-down transistor connected in series between the power supply and the ground, the second pull-up transistor and the second pull-down transistor connected at a second latch node;
wherein gates of the first pull-up transistor and of the first pull-down transistor are driven by the second latch node between the second pull-up transistor and the second pull-down transistor;
wherein gates of the second pull-up transistor and of the second pull-down transistor are driven by the first latch node between the first pull-up transistor and the first pull-down transistor;
a first n-channel pass transistor connected between the first latch node and a first bit line, and having a gate connected to a word line;
a second n-channel pass transistor connected between the second latch node and a second bit line, and having a gate connected to the word line;
a first p-channel pass transistor connected between the first latch node and the first bit line, and having a gate connected to an inverse word line;
a second p-channel pass transistor connected between the second latch node and the second bit line, and having a gate connected to the inverse word line;
a first data transistor with a gate connected to the second latch node, and a channel that conducts current controlled by the gate to a first connecting node; and
a first select transistor having a gate connected to a first select line and a channel connected between the first connecting node and a match line;
wherein the match line is perpendicular to the first select line, wherein the match line connects to other CAM cells in a row and the first select line connects to other CAM cells in a column of an array of the CAM cells arrayed into rows and columns,
further comprising a Ternary Content-Addressable Memory (TCAM) cell that further comprises;
a ternary first pull-up transistor and a ternary first pull-down transistor connected in series between the power supply and the ground, the ternary first pull-up transistor and the ternary first pull-down transistor connected at a ternary first latch node;
a ternary second pull-up transistor and a ternary second pull-down transistor connected in series between the power supply and the ground, the ternary second pull-up transistor and the ternary second pull-down transistor connected at a ternary second latch node;
wherein gates of the ternary first pull-up transistor and of the ternary first pull-down transistor are driven by the ternary second latch node between the ternary second pull-up transistor and the ternary second pull-down transistor;
wherein gates of the ternary second pull-up transistor and of the ternary second pull-down transistor are driven by the ternary first latch node between the ternary first pull-up transistor and the ternary first pull-down transistor;
a ternary first n-channel pass transistor connected between the ternary first latch node and a ternary first bit line, and having a gate connected to the word line;
a ternary second n-channel pass transistor connected between the ternary second latch node and a ternary second bit line, and having a gate connected to the word line;
a first p-channel pass transistor connected between the ternary first latch node and the ternary first bit line, and having a gate connected to the inverse word line;
a ternary second p-channel pass transistor connected between the ternary second latch node and the ternary second bit line, and having a g rate connected to the inverse word line;
a ternary first data transistor with a gate connected to the ternary second latch node, and a channel that conducts current controlled by the gate to a ternary first connecting node; and
a ternary first select transistor having a gate connected to a ternary first select line and a channel connected between the ternary first connecting node and the match line,
wherein a compare operation is performed by applying a compare bit from compare data to the ternary first select line, and by applying an inverse of the e compare bit to the first select line; wherein when the compare bit mismatches data stored in the TCAM cell the match line is discharged through the first select transistor and the first data transistor, or is discharged through the ternary first select transistor and the ternary first data transistor,
wherein for cells in even columns;
the first data transistor and the ternary first data transistor each further comprises an n-channel transistor having a source connected to the ground;
the first select transistor and the ternary first select transistor each further comprises an n-channel transistor;
the match line further comprises a true match line that is precharged high before the compare operation and is discharged low when a mismatch occurs in an even column;
wherein for cells in odd columns;
the first data transistor comprises a p-channel transistor with a source connected to the power supply;
the ternary first data transistor comprises a p-channel transistor with a source connected to the power supply;
the first select transistor and the ternary first select transistor each comprise a p-channel transistor;
the match line is a complement match line that is precharged low before the compare operation and is discharged high when a mismatch occurs in an odd column;
further comprising, for a row of the TCAM cell;
a true precharge transistor that precharges the true match line high before the compare operation;
a complement precharge transistor that precharges the complement match line low before the compare operation;
match logic that signals a match for the row of the TCAM cell when the true match line remains high and the complement match line remains low during the compare operation,
wherein a total number of n-channel transistors equals a total number of p-channel transistors in a pair of the CAM cell, the pair including a CAM cell in the even columns and a CAM cell in the odd columns,
whereby the pair of the CAM cell is P/N balanced.