Power loss protection and reset signal generation in memory systems
The present disclosure relates to methods and apparatuses for power loss protection in a memory system. In one example, a memory system includes a memory device, a controller, a power loss protection (PLP) circuit, and a protection circuit. The controller is coupled to the memory device. A reset terminal of the controller is coupled to a capacitor. The protection circuit is coupled to the controller and the PLP circuit. The protection circuit is configured to: receive a PLP output voltage from the PLP circuit, receive a system supply voltage, and provide a reset signal to the reset terminal of the controller in response to determining that the PLP output voltage is lower than a fraction of the system supply voltage.
1 . A memory system comprising:
a memory device;
a controller coupled to the memory device, wherein a reset terminal of the controller is coupled to a capacitor;
a power loss protection (PLP) circuit configured to provide PLP output voltage with a stable voltage level during a power failure; and
a protection circuit coupled to the controller and the PLP circuit, wherein the protection circuit is configured to:
receive the PLP output voltage from the PLP circuit;
receive a system supply voltage; and
provide a reset signal to the reset terminal of the controller in response to determining that the PLP output voltage is lower than a fraction of the system supply voltage, wherein the protection circuit is configured to pull the reset terminal to ground, by coupling an output of the protection circuit to ground when the PLP output voltage is lower than the fraction of the system supply voltage, to release energy stored in the capacitor due to the power failure.
2 . The memory system according to claim 1 , wherein the capacitor is coupled between the reset terminal of the controller and the ground.
3 . The memory system according to claim 1 , wherein the protection circuit comprises a comparator, a first input of the comparator is coupled to the PLP output voltage, a second input of the comparator is coupled to the fraction of the system supply voltage, and an output of the comparator is coupled to the reset terminal of the controller.
4 . The memory system according to claim 3 , wherein the comparator is an open drain comparator.
5 . The memory system according to claim 3 , wherein the first input of the comparator is coupled to the PLP output voltage through a current-limiting resistor.
6 . The memory system according to claim 3 , wherein the second input of the comparator is coupled to the system supply voltage through a voltage divider comprising two or more resistors, and the voltage divider is configured to generate the fraction of the system supply voltage that is lower than the PLP output voltage in response to at least that the system supply voltage is within a proper working range.
7 . The memory system according to claim 6 , wherein the protection circuit is configured to hold the reset signal below a reset threshold voltage level for a time period, and the time period is increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.
8 . The memory system according to claim 1 , wherein the controller performs one or more initialization operations for the memory device upon receiving the reset signal.
9 . A power protection apparatus comprising:
a controller, wherein a reset terminal of the controller is coupled to a capacitor;
a power loss protection (PLP) circuit configured to provide PLP output voltage with a stable voltage level during a power failure; and
a protection circuit coupled to the controller and the PLP circuit, wherein:
the protection circuit comprises a comparator and is configured to:
receive the PLP output voltage of the PLP circuit;
receive a system supply voltage; and
provide a reset signal to the reset terminal of the controller in response to determining that the PLP output voltage of the PLP circuit is lower than a fraction of the system supply voltage, wherein the protection circuit is configured to pull the reset terminal to ground, by coupling an output of the protection circuit to ground when the PLP output voltage is lower than the fraction of the system supply voltage, to release energy stored in the capacitor due to a power failure;
a first input of the comparator is coupled to the PLP output voltage;
a second input of the comparator is coupled to the fraction of the system supply voltage; and
an output of the comparator is coupled to the reset terminal of the controller.
10 . The power protection apparatus according to claim 9 , wherein the capacitor is coupled between the reset terminal of the controller and the ground.
11 . The power protection apparatus according to claim 10 , wherein the comparator is an open drain comparator.
12 . The power protection apparatus according to claim 10 , wherein the first input of the comparator is coupled to the PLP output voltage through a current-limiting resistor.
13 . The power protection apparatus according to claim 10 , wherein the second input of the comparator is coupled to the system supply voltage through a voltage divider comprising two or more resistors, and the voltage divider is configured to generate the fraction of the system supply voltage that is lower than the PLP output voltage in response to at least that the system supply voltage is within a proper working range.
14 . The power protection apparatus according to claim 13 , wherein the protection circuit is configured to hold the reset signal for a time period, and the time period is increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.
15 . The power protection apparatus according to claim 9 , wherein the controller performs one or more initialization operations for a memory device coupled to the controller upon receiving the reset signal.
16 . A method for resetting a memory system comprising a memory device, a controller, a power loss protection (PLP) circuit, and a protection circuit, the method comprising:
receiving, by the protection circuit, a PLP output voltage from the PLP circuit, wherein the PLP output voltage is provided with a stable voltage level during a power failure;
receiving, by the protection circuit, a system supply voltage; and
providing, by the protection circuit, a reset signal to a reset terminal of the controller in response to determining that the PLP output voltage of the PLP circuit is lower than a fraction of the system supply voltage, wherein the controller is coupled to the memory device, and the reset terminal of the controller is coupled to a capacitor, wherein the protection circuit is configured to pull the reset terminal to ground, by coupling an output of the protection circuit to ground when the PLP output voltage is lower than the fraction of the system supply voltage, to release energy stored in the capacitor due to a power failure.
17 . The method according to claim 16 , wherein the capacitor is coupled between the reset terminal of the controller and the ground.
18 . The method according to claim 16 , wherein the protection circuit comprises a comparator, a first input of the comparator is coupled to the PLP output voltage, a second input of the comparator is coupled to the fraction of the system supply voltage, and an output of the comparator is coupled to the reset terminal of the controller.
19 . The method according to claim 18 , wherein the comparator is an open drain comparator.
20 . The method according to claim 18 , wherein the second input of the comparator is coupled to the system supply voltage through a voltage divider comprising two or more resistors, the voltage divider is configured to generate the fraction of the system supply voltage that is lower than the PLP output voltage in response to at least that the system supply voltage is within a proper working range, the protection circuit is configured to hold the reset signal for a time period, and the time period is increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.