Cross temperature NAND read adjustment
Technology for re-calibrating a temperature coefficient (Tco) for reading NAND memory cells. The Tco may be re-calibrated based on an amount of data retention impact to NAND memory cells since the NAND memory cells were programmed. The data retention impact may be measured by determining a shift to a candidate Vt distribution. The candidate Vt distribution may be selected as one that exhibits a significant data retention impact. The Tco may include, but is not limited to a bit line voltage Tco or a Vread Tco. The bit line voltage Tco may be used to establish the bit line voltage during read. The Vread Tco may be used to establish a voltage to unselected word lines during read.
1 . An apparatus comprising:
one or more control circuits configured to connect to a NAND memory structure, the NAND memory structure having blocks having NAND strings and word lines associated with the NAND strings, the NAND memory structure having bit lines associated with the NAND strings, the one or more control circuits configured to:
measure a data retention impact to a data state of a group of NAND memory cells in a selected block of NAND memory cells since the group was programmed to the data state, including determining an amount of a downshift of a lower tail of a candidate threshold voltage distribution of a plurality of threshold voltage distributions to which the group of NAND memory cells were programmed;
set a temperature coefficient (Tco) based on the amount of the downshift of the lower tail of the candidate threshold voltage distribution; and
read NAND memory cells in the selected block based on the set Tco and a present temperature.
2 . The apparatus of claim 1 , wherein:
the temperature coefficient (Tco) includes a bit line Tco for a bit line voltage during read; and
the one or more control circuits are configured to apply a voltage to the bit lines during the read of the NAND memory cells in the selected block based on the set Tco and the present temperature, wherein a magnitude of the bit line voltage depends on the bit line Tco and the present temperature.
3 . The apparatus of claim 1 , wherein:
the temperature coefficient (Tco) includes a read pass Tco for a read pass voltage during read; and
the one or more control circuits are configured to apply a voltage to unselected word lines in the selected block during the read of the NAND memory cells in the selected block based on the set Tco and the present temperature, wherein a magnitude of the unselected word line voltage depends on the read pass Tco and the present temperature.
4 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
read the group of memory cells at two voltage levels associated with the lower tail of the candidate threshold voltage distribution of the plurality of threshold voltage distributions;
determine how many memory cells in the group have a threshold voltage between the two voltage levels to determine the amount of the downshift of the lower tail to determine the data retention impact in the group; and
set the Tco based on how many memory cells in the group have a threshold voltage between the two voltage levels in order to set the Tco based on the amount of the downshift of the lower tail.
5 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
perform a valley scan search during the read of the NAND memory cells in the selected block based on the set Tco and the present temperature, the valley scan search comprising reading at a plurality of read levels associated with a data state; and
determine a new read level for the data state based on a read level in the valley scan search having a lowest fail bit count (FBC).
6 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
dynamically update read levels based on the read of the NAND memory cells in the selected block based on the set Tco and the present temperature; and
read NAND memory cells in the selected block based on the dynamically updated read levels, the set Tco, and the present temperature.
7 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
perform a bitscan of the group of NAND memory cells in the selected block to determine a bitscan count that determines the downshift of the lower tail of the candidate threshold voltage distribution to indicate the data retention impact;
access a table from non-transitory memory, wherein the table comprises entries that associate bitscan count ranges to modifications to the Tco; and
set the Tco based on the bitscan count determined from the bitscan.
8 . A method for operating non-volatile storage, the method comprising:
determining a bit line voltage temperature coefficient (Tco) based on a shift to a candidate threshold voltage distribution to which a group of NAND memory cells in the non-volatile storage were programmed, the NAND memory cells associated with a set of bit lines in the non-volatile storage, including establishing the bit line voltage Tco based on how many memory cells in the group have a threshold voltage between two voltage levels associated with a lower tail of the candidate threshold voltage distribution;
applying a bit line voltage to the set of bit lines that has a magnitude based on the bit line voltage Tco and a present temperature; and
reading selected NAND memory cells associated with the set of bit lines while applying the bit line voltage to the set of bit lines.
9 . The method of claim 8 , wherein:
the group of NAND memory cells reside in a selected block; and
reading the selected NAND memory cells associated with the set of bit lines while applying the bit line voltage to the set of bit lines includes reading NAND memory cells in the selected block other than the group of NAND memory cells.
10 . The method of claim 8 , further comprising accessing a default bit line voltage Tco for freshly programmed memory cells that are programmed to a plurality of threshold voltage distribution including the candidate threshold voltage distribution, wherein the default bit line voltage Tco assumes no shift to the candidate threshold voltage distribution;
wherein determining the bit line voltage Tco based on the shift to the candidate threshold voltage distribution to which the group of NAND memory cells in the non-volatile storage were programmed includes re-calibrating the default bit line voltage Tco to account for effects of data retention on the group of NAND memory cells.
11 . A non-volatile memory system, comprising:
a NAND memory structure having NAND memory cells, bit lines associated with the NAND memory cells and word lines associated with the NAND memory cells; and
one or more control circuits in communication with the NAND memory structure, the one or more control circuits configured to:
program NAND memory cells in a selected block to a plurality of threshold voltage distributions;
determine a number of first NAND memory cells in the selected block having a threshold voltage within a voltage range in a lower tail of a candidate threshold voltage distribution of the plurality of threshold voltage distributions;
determine a bit line voltage temperature coefficient (Tco) based on the number of first NAND memory cells having a threshold voltage within the voltage range;
read the first NAND memory cells in the selected block while applying a first voltage to the bit lines that is based on the bit line voltage Tco and a first present temperature; and
read second NAND memory cells in the selected block while applying a second voltage that is based on the bit line voltage Tco and a second present temperature.
12 . The non-volatile memory system of claim 11 , wherein the one or more control circuits are configured to:
access a table from non-transitory memory, wherein the table comprises entries that associate bitscan count ranges to modifications to a default bit line voltage Tco, the bitscan count being a number of memory cells having a threshold voltage within the voltage range in the lower tail of the candidate threshold voltage distribution;
select an entry in the table that corresponds to the number of the first NAND memory cells in the selected block having a threshold voltage within the voltage range in the lower tail of the candidate threshold voltage distribution; and
determine the bit line voltage Tco based on the modification to the bit line voltage Tco in the selected entry.
13 . The non-volatile memory system of claim 11 , wherein the one or more control circuits are configured to:
determine a Vread temperature coefficient (Tco) based on the number of the first NAND memory cells having a threshold voltage within the voltage range;
apply a voltage to unselected word lines in the selected block that is based on the Vread Tco and a third present temperature; and
read third NAND memory cells in the selected block while applying the voltage that is based on the Vread Tco and the third present temperature to the unselected word lines.
14 . The non-volatile memory system of claim 11 , wherein the one or more control circuits are configured to:
dynamically update read levels based on the read of the second NAND memory cells in the selected block while applying the second voltage that is based on the bit line voltage Tco and the second present temperature to the bit lines; and
read third NAND memory cells in the selected block based on the dynamically updated read levels, the bit line voltage Tco, and a third present temperature.