Sense amplifier control
A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.
1 . A sense amplifier system, comprising:
a precharge transistor connected between a power input terminal and a reference input node and having a gate terminal;
a reference transistor connected between the reference input node and a ground terminal and having a second gate terminal;
a NAND circuit having a first input terminal connected to the reference input node, a second input terminal connected to the power input terminal, and a trigger output terminal;
wherein in a precharge phase, the precharge transistor is configured to receive a precharge signal via the gate terminal; and
wherein in a sensing phase subsequent to the precharge phase, the NAND circuit is configured to output a triggering signal at the trigger output terminal in response to the reference input node reaching a triggering level.
2 . The sense amplifier system of claim 1 , further comprising one or more sense amplifiers coupled to the trigger output terminal, the one or more sense amplifiers configured to latch a received data signal in response to receiving the triggering signal.
3 . The sense amplifier system of claim 2 , wherein at least one sense amplifier of the one or more sense amplifiers includes a latch circuit having a trigger input terminal configured to receive the triggering signal, and a data input terminal configured to receive data signals.
4 . The sense amplifier system of claim 2 , wherein at least one sense amplifier of the one or more sense amplifiers includes a pulse generator circuit configured to output a pulse signal in response to receiving the triggering signal.
5 . The sense amplifier system of claim 4 , wherein the at least one sense amplifier of the one or more sense amplifiers includes an input circuit coupled to a memory cell and the pulse generator circuit, wherein the input circuit is configured to output a data signal from the memory cell in response to receiving the pulse signal.
6 . The sense amplifier system of claim 1 , wherein the triggering level is less than a precharge level.
7 . The sense amplifier system of claim 1 , wherein the precharge transistor is a p-channel metal-oxide semiconductor (PMOS) transistor.
8 . The sense amplifier system of claim 1 , wherein the reference transistor is configured to receive a word line signal via the second gate terminal.
9 . The sense amplifier system of claim 1 , wherein in the precharge phase, the precharge transistor precharges a data input node of a memory cell to a predetermined precharge level in response to the precharge signal.
10 . The sense amplifier system of claim 9 , wherein in the sensing phase, a voltage level of the data input node falls at a first rate based on a logic 0 being stored in the memory cell, or the voltage level of the data input node falls at a second rate based on a logic 1 being stored in the memory cell, wherein a voltage level of the reference input node falls at a third rate, the third rate between the first rate and the second rate.
11 . A memory device, comprising:
a memory cell configured to store data;
a word line coupled to the memory cell and configured to receive a word line signal;
a bit line coupled to the memory cell and configured to receive a data signal from the memory cell;
a sense amplifier coupled to the bit line and configured to latch the data signal received on the bit line; and
a sense amplifier control circuit, including:
a precharge transistor connected between a power input terminal and a reference input node and having a gate terminal;
a reference transistor connected between the reference input node and a ground terminal and having a second gate terminal;
a NAND circuit having a first input terminal connected to the reference input node, a second input terminal connected to the power input terminal, and a trigger output terminal;
wherein in a precharge phase, the precharge transistor is configured to receive a precharge signal via the gate terminal;
wherein in a sensing phase subsequent to the precharge phase, the NAND circuit is configured to output a triggering signal at the trigger output terminal in response to the reference input node reaching a triggering level; and
wherein the sense amplifier control circuit is coupled to the sense amplifier via the trigger output terminal.
12 . The memory device of claim 11 , wherein the sense amplifier includes:
a latch circuit having a trigger input terminal configured to receive the triggering signal;
a pulse generator circuit configured to output a pulse signal in response to the triggering signal; and
an input circuit coupled to the memory cell and the pulse generator circuit and configured to output the data signal to the latch circuit in response to the pulse signal.
13 . The memory device of claim 11 , further comprising:
one or more additional memory cells;
one or more additional bit lines, each of the one or more additional memory cells coupled to a respective bit line of the one or more additional bit lines; and
one or more additional sense amplifiers, wherein the sense amplifier control circuit is configured to output the triggering signal to the sense amplifier and the one or more additional sense amplifiers.
14 . The memory device of claim 11 , wherein in the precharge phase, the precharge transistor precharges a data input node of the memory cell to a predetermined precharge level in response to the precharge signal.
15 . The memory device of claim 14 , wherein in the sensing phase, a voltage level of the data input node falls at a first rate based on a logic 0 being stored in the memory cell, or the voltage level of the data input node falls at a second rate based on a logic 1 being stored in the memory cell, wherein a voltage level of the reference input node falls at a third rate, the third rate between the first rate and the second rate.
16 . The memory device of claim 14 , wherein the triggering level is less than the predetermined precharge level.
17 . A method, comprising:
storing a data signal in a memory cell;
receiving a precharge signal;
in response to the precharge signal, precharging a reference input node of a trigger circuit and a data input node of a sense amplifier to a predetermined precharge level;
in response to the reference input node falling from the predetermined precharge level to a triggering level, outputting a triggering signal to the sense amplifier to cause the sense amplifier to latch the data signal;
wherein after precharging the reference input node, a voltage level of the data input node falls at a first rate based on the data signal comprising a logic 0, or the voltage level of the data input node falls at a second rate based on the data signal comprising a logic 1, and
wherein a voltage level of the reference input node falls at a third rate, the third rate between the first rate and the second rate.
18 . The method of claim 17 , further comprising outputting the triggering signal to one or more additional sense amplifiers.
19 . The method of claim 17 , wherein the trigger circuit includes a NAND circuit having a first input terminal coupled to the reference input node, a second input terminal configured to receive a power input signal, and a trigger output terminal configured to output the triggering signal.
20 . The method of claim 17 , wherein the trigger circuit includes an inverter circuit including a first input terminal coupled to the reference input node and a trigger output terminal configured to output the triggering signal.