Apparatus for controlling NAND flash memory device and method for controlling same

1 . A control apparatus for a NAND flash memory device, comprising:

a NAND flash memory;

a controller configured to generate a command signal to program, read, and erase data in the NAND flash memory when a voltage level of a supply power is a first level; and

an auxiliary power circuit configured to maintain power for operating the NAND flash memory and the controller during a first time period from a first time point when the voltage level of the supply power becomes less than or equal to a second level which is smaller than the first level,

wherein the controller is configured to block the command signal during the first time period,

wherein power supplied to the NAND flash memory is blocked regardless of the voltage level of the supply power for at least a second time period from a second time point after the first time period has elapsed, and

wherein power is blocked from being supplied to the NAND flash memory by the controller when the voltage level of the supply power maintains the first level before the second time period elapses from the second time point, and

wherein the controller sequentially performs a power-off sequence and a power-on sequence when the voltage level of the supply power maintains the first level after the second time period has elapsed from the second time point.

2 . The control apparatus of claim 1 , wherein when the first time point is a program operation time (tPROG) or an erase operation time (tBERS) of the NAND flash memory, the auxiliary power circuit supplies auxiliary power for completing the program operation or erase operation of the NAND flash memory.

3 . The control apparatus of claim 2 , wherein when the first time point is in an electronic movement based on the program operation time (tPROG) or the erase operation time (tBERS) of the NAND flash memory, the auxiliary power circuit is configured to supply the auxiliary power for completing the program operation or erase operation of the NAND flash memory.

4 . The control apparatus of claim 1 , wherein the first time period is a time until a program operation or an erase operation being performed in the NAND flash memory before the first time point is reached.

5 . The control apparatus of claim 1 , further comprising:

a power management IC (PMIC) connected to the supply power and supplying power to the NAND flash memory and the controller.

6 . The control apparatus of claim 5 , wherein the auxiliary power circuit is disposed between the PMIC and the NAND flash memory.

7 . The control apparatus of claim 5 , wherein the controller is configured to control the PMIC so that power is supplied to the NAND flash memory after the power supply is blocked for the at least second time period.

8 . The control apparatus of claim 5 , further comprising:

an input voltage detector configured to detect a voltage level of the supply power, and

wherein the auxiliary power circuit is connected to a power input terminal of the PMIC.

9 . The control apparatus of claim 8 , wherein the input voltage detector is configured to detect a voltage level of an input terminal of the auxiliary power circuit.

10 . The control apparatus of claim 8 , further comprising:

a detection signal transmitter configured to transmit the voltage level detected through the input voltage detector to the controller.

11 . The control apparatus of claim 10 , wherein the detection signal transmitter includes a first resistor, a second resistor, a third resistor, and a transistor.

12 . The control apparatus of claim 11 , wherein one end of the first resistor is connected to an output terminal of the input voltage detector,

wherein an other end of the first resistor is connected to one end of the third resistor and a base of the transistor,

wherein one end of the second resistor is connected to a power terminal of the supply power,

wherein an other end of the second resistor is connected to a collector of the transistor and a signal input terminal of the controller,

wherein one end of the third resistor is connected to the one end of the first resistor and the base of the transistor; and

wherein an other end of the third resistor is connected to an emitter and a ground terminal of the transistor.

13 . The control apparatus of claim 5 , further comprising:

a regulator disposed between the supply power and the PMIC;

wherein the auxiliary power circuit is disposed between the regulator and the PMIC.

14 . The control apparatus of claim 1 , wherein the controller is configured to ignore a voltage change of the supply power in an ACC ON state.

15 . The control apparatus of claim 1 , wherein when the voltage level of the supply power is greater than or equal to the first level for a third time period from a third time point after the second time period, the controller is configured to supply power to the NAND flash memory.

16 . The control apparatus of claim 1 , wherein when a predetermined time has elapsed from a point in time when ACC OFF is detected, the controller is configured to operate memory protection function based on a change in voltage level of the supply power.

17 . A method for controlling a NAND flash memory device, comprising:

detecting a voltage level of a supply power;

generating a command signal to program, read, and erase data in a NAND flash memory when the voltage of the supply power is a first level;

stopping access to the NAND flash memory when the detected voltage level is less than or equal to a second level which is smaller than the first level;

supplying auxiliary power to the NAND flash memory and a controller for a first time period from a first time point when the detected voltage level becomes less than or equal to the second level;

blocking the auxiliary power supplied to the NAND flash memory regardless of the voltage level of the supply power for at least a second time period from a second time point after the first time period has elapsed; and

sequentially performing a power-off sequence and a power-on sequence when the voltage level of the supply power maintains the first level after the second time period has elapsed from the second time point,

wherein the stopping of the access comprises:

blocking a command signal for controlling the NAND flash memory, and

wherein power is blocked from being supplied to the NAND flash memory by the controller when the voltage level of the supply power maintains the first level before the second time period elapses from the second time point.

18 . The method of claim 17 , wherein the supplying of the auxiliary power comprises:

Supplying the auxiliary power for completion of a program operation or an erase operation of the NAND flash memory when the first time point is a program operation time (tPROG) or an erase operation time (tBERS) of the NAND flash memory.

19 . The method of claim 18 , wherein the first time period is a time until the program operation or the erase operation being performed in the NAND flash memory before the first time point is reached.