Method of operating a three-dimensional semiconductor memory device

1 . A method of programming a three-dimensional semiconductor memory device,

wherein the three-dimensional semiconductor memory device comprises:

word lines extending in a first direction and stacked in a third direction, the first direction being parallel to a top surface of a substrate, the third direction being perpendicular to the top surface of the substrate;

vertical channel structures that pass through the word lines, wherein each of the vertical channel structures includes a back-gate electrode, a channel layer, and a memory layer;

a common source line electrically connected to a first end of the channel layer of each of the vertical channel structures;

bit lines extending in a second direction, each of the bit lines being electrically connected to a second end of the channel layer of each of the vertical channel structures, the second direction crossing the first direction and parallel to the top surface of the substrate; and

a back-gate line electrically connected to a first end of the back-gate electrode of each of the vertical channel structures,

wherein the method comprises:

applying a first word line programming voltage to a selected word line among the word lines, floating unselected word lines among the word lines, and applying a back-gate pass voltage to the back-gate electrode in a first programming step;

applying a first word line verification voltage to the selected word line, applying a word line pass voltage to the unselected word lines, and

applying a first back-gate verification voltage to the back-gate electrode in a first verification step;

applying a second word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode in a second programming step; and

applying a second word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a second back-gate verification voltage to the back-gate electrode in a second verification step,

wherein the second word line programming voltage is greater than the first word line programming voltage, and

the second back-gate verification voltage is lower than the first back-gate verification voltage.

2 . The method of claim 1 , further comprising:

applying a third word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode in a third programming step; and

applying a third word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a third back-gate verification voltage to the back-gate electrode in a third verification step,

wherein the third word line programming voltage is greater than the second word line programming voltage, and

the third back-gate verification voltage is lower than the second back-gate verification voltage.

3 . The method of claim 2 , further comprising:

applying a fourth word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode in a fourth programming step; and

applying a fourth word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a fourth back-gate verification voltage to the back-gate electrode in a fourth verification step,

wherein the fourth word line programming voltage is greater than the third word line programming voltage, and

the fourth back-gate verification voltage is lower than the third back-gate verification voltage.

4 . The method of claim 1 , further comprising, in each of the first programming step and the second programming step:

applying a bit line programming voltage to a selected bit line among the bit lines, and

applying a turn-on voltage to unselected bit lines among the bit lines,

wherein the bit line programming voltage is a negative voltage, and

the turn-on voltage is lower than the word line pass voltage.

5 . The method of claim 1 ,

wherein the word lines include:

a drain selection line disposed closest to the bit line; and

a source selection line disposed closest to the common source line,

wherein the method further comprises, in each of the first programming step and the second programming step:

applying a turn-on voltage to the drain selection line;

applying the word line pass voltage to the source selection line; and

applying a ground voltage to the common source line.

6 . The method of claim 1 , further comprising, in each of the first verification step and the second verification step:

applying a bit line verification voltage to a selected bit line among the bit lines; and

applying a ground voltage to unselected bit lines among the bit lines,

wherein the bit line verification voltage is a positive voltage lower than the word line pass voltage.

7 . The method of claim 1 ,

wherein the word lines include:

a drain selection line disposed closest to the bit line; and

a source selection line disposed closest to the common source line,

wherein the method further comprises, in each of the first verification step and the second verification step:

applying the word line pass voltage to the drain selection line; and

floating the source selection line and the common source line.

8 . A method of reading a three-dimensional semiconductor memory device,

wherein the three-dimensional semiconductor memory device comprises:

word lines extending in a first direction and stacked in a third direction, the first direction being parallel to a top surface of a substrate, the third direction being perpendicular to the top surface of the substrate;

vertical channel structures that pass through the word lines, wherein each of the vertical channel structures includes a back-gate electrode, a channel layer, and a memory layer;

a common source line electrically connected to a first end of the channel layer of each of the vertical channel structures;

bit lines extending in a second direction, each of the bit lines being electrically connected to a second end of the channel layer of each of the vertical channel structures, the second direction crossing the first direction and parallel to the top surface of the substrate; and

a back-gate line electrically connected to a first end of the back-gate electrode of each of the vertical channel structures,

wherein the method comprises:

applying a word line read voltage to a selected word line among the word lines;

applying a word line pass voltage to unselected word lines among the word lines; and

applying a back-gate read voltage to the back-gate electrode of each of the vertical channel structures,

wherein the word line read voltage includes a plurality of pulses that change from an initial word line read voltage of a negative voltage to a final word line read voltage of a positive voltage, and

the final word line read voltage is lower than the word line pass voltage.

9 . The method of claim 8 , wherein the back-gate read voltage includes a plurality of pulses that change from an initial back-gate read voltage of a positive voltage to a final back-gate read voltage of a negative voltage.

10 . The method of claim 9 , wherein the word line read voltage and the back-gate read voltage are different from each other at a same time.

11 . The method of claim 8 , wherein the back-gate read voltage has a positive voltage lower than the word line pass voltage.

12 . The method of claim 8 , further comprising:

applying a bit line read voltage to a selected bit line among the bit lines; and

applying a ground voltage to unselected bit lines among the bit lines,

wherein the bit line read voltage is a positive voltage lower than the word line pass voltage.

13 . The method of claim 8 ,

wherein the word lines include:

a drain selection line disposed closest to the bit line; and

a source selection line disposed closest to the common source line,

wherein the method further comprises:

applying the word line pass voltage to the drain selection line; and

floating the source selection line and the common source line.

14 . A method of reading a three-dimensional semiconductor memory device,

wherein the three-dimensional semiconductor device comprises:

a plurality of word lines extending in a first direction and stacked in a third direction, the first direction being parallel to a top surface of a substrate, the third direction being perpendicular to the top surface of the substrate;

vertical channel structures that pass through the plurality of word lines, wherein each of the vertical channel structures includes a back-gate electrode, a channel layer, and a memory layer;

a common source line electrically connected to a first end of the channel layer of each of the vertical channel structures;

bit lines extending in a second direction, each of the bit lines being electrically connected to a second end of the channel layer of each of the vertical channel structures, the second direction crossing the first direction and parallel to the top surface of the substrate; and

a back-gate line electrically connected to a first end of the back-gate electrode of each of the vertical channel structures,

wherein the method comprises:

applying a word line read voltage to a selected word line among the plurality of word lines;

applying a word line pass voltage to unselected word lines among the plurality of word lines, and

applying a back-gate read voltage to the back-gate electrode,

wherein the back-gate read voltage includes a plurality of pulses that change from an initial back-gate read voltage of a positive voltage to a final back-gate read voltage of a negative voltage; and

wherein the initial back-gate read voltage is lower than the word line pass voltage.

15 . The method of claim 14 , wherein the word line read voltage includes a plurality of pulses that change from an initial word line read voltage of a negative voltage to a final word line read voltage of a positive voltage.

16 . The method of claim 15 , wherein the word line read voltage and the back-gate read voltage are different from each other at a same time.

17 . The method of claim 14 , further comprising:

applying a bit line read voltage to a selected bit line among the bit lines; and

applying a ground voltage to unselected bit lines among the bit lines,

wherein the bit line read voltage is a positive voltage lower than the word line pass voltage.

18 . The method of claim 14 ,

wherein each of the plurality of word lines includes:

a drain selection line disposed closest to the bit lines; and

a source selection line disposed closest to the common source line,

wherein the method further comprises:

applying the word line pass voltage to the drain selection line; and

floating the source selection line and the common source line.