Clock generation circuits for memory devices with built-in self test
A circuit includes one or more functional circuits, and a clock generation circuit operatively coupled to the one or more functional circuits. The clock generation circuit is configured to: receive a control signal to switch the one or more functional circuits between a first operation mode and a second operation mode; receive a first clock signal and a second clock signal corresponding to the first operation mode and the second operation mode, respectively; and output, to the one or more functional circuits, a clock pulse signal based on either the first clock signal or the second clock signal. The clock generation circuit is configured to generate either a first conduction path to output the clock pulse signal or a second conduction path to output the clock pulse signal. Each of the first and second conduction paths includes a predefined number of gate delays.
1 . An integrated circuit, comprising:
one or more functional circuits; and
a clock generation circuit operatively coupled to the one or more functional circuits and configured to:
directly receive a control signal to switch the one or more functional circuits between a first operation mode and a second operation mode, wherein the second operation mode is a built-in self-test mode;
directly receive a first clock signal and a second clock signal corresponding to the first operation mode and the second operation mode, respectively;
generate at least one of a first conduction path according to the first clock signal or a second conduction path according to the second clock signal, wherein each of the first and second conduction paths includes a predefined number of gate delays that is equal to or less than 2; and
output, to the one or more functional circuits via at least one of the first conductive path or the second conductive path formed through at least one transistor and an inverter, a clock pulse signal based on at least one of the first clock signal or the second clock signal.
2 . The integrated circuit of claim 1 , wherein the one or more functional circuits include a decoder circuit, a word line driver circuit, a memory array, an input/output circuit, or combinations thereof.
3 . The integrated circuit of claim 1 , wherein the clock generation circuit comprises:
a first switch logic circuit configured to directly receive the first clock signal and a logic inverse of the control signal;
a second switch logic circuit configured to directly receive the second clock signal and the control signal; and
the inverter operatively coupled to the first switch logic circuit and second switch logic circuit, and configured to output the clock pulse signal.
4 . The integrated circuit of claim 3 , wherein, when the logic inverse of the control signal is asserted, the first conduction path is formed to travel through a first logic gate of the first switch logic circuit and the inverter, and wherein, when the control signal is asserted, the second conduction path is formed to travel through a second logic gate of the second switch logic circuit and the inverter.
5 . The integrated circuit of claim 4 , wherein the first logic gate and the second logic gate are each a transistor.
6 . The integrated circuit of claim 4 , wherein the first logic gate and the second logic gate are each a transmission gate.
7 . The integrated circuit of claim 1 , wherein the clock generation circuit comprises:
a first switch logic circuit configured to receive the control signal and a clock enable signal, and generate a first version of the clock enable signal;
a second switch logic circuit configured to receive a logic inverse of the control signal and the clock enable signal, and generate a second version of the clock enable signal;
a first transistor configured to directly receive the first clock signal;
a second transistor configured to directly receive the second clock signal; and
the inverter operatively coupled to the first transistor and second transistor, and configured to output the clock pulse signal.
8 . The integrated circuit of claim 7 , wherein, when the first version of the clock enable signal is asserted, the first conduction path is formed to travel through the first transistor and the inverter, and wherein, when the second version of the clock enable signal is asserted, the second conduction path is formed to travel through the second transistor and the inverter.
9 . The integrated circuit of claim 7 , wherein the first switch logic circuit and the second switch logic circuit each include a NOR gate receiving a logic inverse of the clock enable signal.
10 . The integrated circuit of claim 7 , wherein the first switch logic circuit and the second switch logic circuit each include another inverter coupling between the clock enable signal and ground.
11 . The integrated circuit of claim 7 , wherein the first switch logic circuit and the second switch logic circuit each include a transmission gate receiving the clock enable signal.
12 . A memory circuit, comprising:
a clock generation circuit configured to:
directly receive, at a first input of the clock generation circuit, a control signal to switch a corresponding memory circuit between a first operation mode and a second operation mode;
directly receive, at a second input of the clock generation circuit, a first clock signal corresponding to the first operation mode;
directly receive, at a third input of the clock generation circuit, a second clock signal corresponding to the second operation mode;
form, through at least one transistor and an inverter, at least one of a first conductive path according to the first clock signal or a second conductive path according to the second clock signal, wherein the first conduction path extends from the second input to an output of the clock generation circuit and the second conduction path extends from the third input to the output, and wherein the first and second conduction paths each have a number of gate delays that is equal to or less than 2; and
output, at the output of the clock generation circuit, a clock pulse signal through the at least one transistor and the inverter of at least one of the first conduction path or the second conduction path.
13 . The memory circuit of claim 12 , wherein, between the second input to the output, the first conduction path extends through a first transistor and an inverter of the clock generation circuit, wherein, between the third input to the output, the second conduction path extends through a second transistor and the inverter of the clock generation circuit, and wherein the first transistor has a first gate configured to receive the first clock signal, and the second transistor has a second gate configured to receives the second clock signal.
14 . The memory circuit of claim 13 , wherein the first conduction path or second conduction path is formed based on a combination of a clock enable signal and the control signal.
15 . The memory circuit of claim 12 , wherein, between the second input to the output, the first conduction path extends through a first transmission gate and an inverter of the clock generation circuit, wherein, between the third input to the output, the second conduction path extends through a second transmission gate and the inverter of the clock generation circuit, and wherein the first transmission gate configured to receive the first clock signal, and the second transmission gate configured to receive the second clock signal.
16 . The memory circuit of claim 15 , wherein the first conduction path or second conduction path is formed based on a combination of a clock enable signal and the control signal.
17 . The memory circuit of claim 12 , wherein the first operation mode includes a read/write operation of the corresponding memory circuit, and the second operation mode includes a built-in self-test mode of the corresponding memory circuit.
18 . A method for operating a memory circuit, comprising:
receiving, directly at a first input of a clock generation circuit, a control signal to switch a corresponding memory circuit between a first operation mode and a second operation mode, wherein the first operation mode includes a read/write operation of the corresponding memory circuit, and the second operation mode includes a built-in self-test mode of the corresponding memory circuit;
receiving, directly at a second input of the clock generation circuit, a first clock signal corresponding to the first operation mode;
receiving, directly at a third input of the clock generation circuit, a second clock signal corresponding to the second operation mode;
generating, through at least one transistor and an inverter, at least one of a first conduction path according to the first clock signal or a second conduction path according to the second clock signal, wherein the first conduction path extends from the second input to an output of the clock generation circuit and the second conduction path extends from the third input to the output, and wherein the first and second conduction paths each have a predefined number of gate delays that is equal to or less than 2; and
outputting, at the output of the clock generation circuit, a clock pulse signal through the at least one transistor and the inverter of at least one of the first conduction path or the second conduction path.
19 . The method of claim 18 , wherein at least one of the first conduction path or the second conduction path is formed based on a combination of a clock enable signal and the control signal.
20 . The method of claim 18 , wherein outputting the clock pulse signal comprises:
outputting, at the output of the clock generation circuit to one or more functional circuits, the clock pulse signal through the at least one transistor and the inverter of at least one of the first conduction path or the second conduction path, wherein the one or more functional circuits comprises a decoder circuit, a word line driver circuit, a memory array, an input/output circuit, or combinations thereof.