Scannable memory subsystem
A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.
1 . A semiconductor memory subsystem, comprising:
an array of memory cells including a scan chain having a first chain segment that includes N memory cells of the array of memory cells, wherein N is an integer number greater than 1; and
a sequence generator having a scan clock input (a SCLK input) and at least N−1 scan sub-clock outputs, wherein the at least N−1 scan sub-clock outputs are respectively coupled to one of the N memory cells in the first chain segment, and wherein the sequence generator, in response to receiving a pulse in a signal on the SCLK input (an SCLK signal), generates a sequence of non-overlapping pulses that are sent to the at least N−1 scan sub-clock outputs with a single pulse of the sequence of non-overlapping pulses on each of the at least N−1 scan sub-clock outputs; and
wherein a total duration of the sequence of non-overlapping pulses is equal to or less than a total duration of a cycle of the SCLK signal.
2 . The semiconductor memory subsystem of claim 1 , wherein one of the N memory cells is configured to receive the signal on the SCLK input on a flush input (FSH or/FSH) and N−1 of the N memory cells have flush inputs (FSH or/FSH) respectively coupled with N−1 of the at least N−1 scan sub-clock outputs, and wherein the pulse in the signal on the SCLK input is included in the sequence of non-overlapping pulses.
3 . The semiconductor memory subsystem of claim 1 , wherein:
each memory cell includes at most one latch;
the memory cells are arranged in rows and columns; and
a row of the memory cells stores a data line including one or more data bytes.
4 . The semiconductor memory subsystem of claim 1 , wherein:
the first chain segment is included in a row of the memory cells.
5 . The semiconductor memory subsystem of claim 1 , wherein:
the first chain segment is included in a column of the memory cells.
6 . The semiconductor memory subsystem of claim 2 , wherein:
the scan chain further includes a second chain segment, including M of the memory cells; and
at least a part of the sequence of non-overlapping pulses is applied to the memory cells in the first chain segment and at least a part of the sequence of non-overlapping pulses is applied to the memory cells in the second chain segment.
7 . The semiconductor memory subsystem of claim 6 , wherein the first chain segment and the second chain segment are separated by a segment buffer memory cell.
8 . The semiconductor memory subsystem of claim 6 , wherein an input buffer of the array of memory cells includes a segment buffer memory cell.
9 . The semiconductor memory subsystem of claim 1 , wherein:
during the cycle of the signal on the SCLK input, bits stored in all memory cells in the scan chain are shifted one position in a direction from a scan chain input to a scan chain output;
the first chain segment includes a first memory cell and a second memory cell;
an output of the first memory cell is directly connected to an input of the second memory cell;
the first memory cell has a first flush input configured to receive a first non-overlapping pulse and the second memory cell has a flush input configured to receive a second non-overlapping pulse; and
the second non-overlapping pulse is earlier during the cycle of the signal on the SCLK input than the first non-overlapping pulse.
10 . The semiconductor memory subsystem of claim 1 , wherein:
a memory cell has a data input (DI), a data output (DO), a scan input (SI), a scan output (SO), a scan enable input (SE), and a flush input (FSH); and
a memory cell includes exactly one latch.
11 . The semiconductor memory subsystem of claim 10 , wherein:
the memory cell further includes a scan input multiplexer with a first input coupled with the data input (DI), a second input coupled with the scan input (SI), a mux output coupled with a data input of the latch, and a select input coupled with the scan enable input (SE); and
the scan input multiplexer is configured to couple the mux output with the data input (DI) when the scan enable input (SE) is deasserted and to couple the mux output with the scan input (SI) when the scan enable input (SE) is asserted.
12 . The semiconductor memory subsystem of claim 1 , wherein:
a memory cell includes exactly one latch, configured as a static random-access memory cell (an SRAM cell).
13 . The semiconductor memory subsystem of claim 1 , wherein the sequence generator comprises:
a pulse shaper to derive a short pulse from the signal on the SCLK input; and
a multi-tap delay line to provide the at least N−1 scan sub-clock outputs, and with an input coupled with an output of the pulse shaper.
14 . The semiconductor memory subsystem of claim 1 , wherein the sequence generator comprises:
one of a frequency-locked loop (FLL), a phase-locked loop (PLL), and a delay-locked loop (DLL), with an input configured to receive the signal on the SCLK input; and
a clock divider with multiple outputs to provide the at least N−1 scan sub-clock outputs, and with an input coupled with the FLL, PLL, or DLL.
15 . The semiconductor memory subsystem of claim 1 , further comprising:
a multiplexer having a first input coupled with an output of a third chain segment, a second input coupled with an output of a fourth chain segment, and an output coupled with a scan input of a fifth chain segment, wherein the multiplexer is configured to select either an output signal of the third chain segment or an output signal of the fourth chain segment.