Hybrid scan chains with flip-flops and latches
An electronic circuit features a hybrid scan chain design comprising a flip-flop-based part of the scan chain and a latch-based part of the scan chain. The latch-based part may be included in an array of memory cells and includes one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The circuit includes a memory element interfacing the scan out (SO) output of the flip-flop-based scan chain with the scan in (SI) input of the latch-based scan chain. The memory element captures and retains the value of the final flip-flop in the flip-flop-based scan chain, enabling subsequent access by the initial latch in the latch-based scan chain without loss of data.
1 . An electronic circuit comprising a flip-flop-based scan chain coupled with a latch-based scan chain, the electronic circuit further comprising:
a memory element coupled between a scan out (SO) output of the flip-flop-based scan chain and a scan in (SI) input of the latch-based scan chain;
wherein:
the latch-based scan chain comprises a chain of scannable latches;
the memory element is configured to capture a value of a last flip-flop in the flip-flop-based scan chain and store the value for access by a first latch in the latch-based scan chain.
2 . The electronic circuit of claim 1 , wherein the memory element is an interface latch with a flush input (FSH input) that is asserted when a clock input (a CLK input) of a flip-flop in the flip-flop-based scan chain is de-asserted, and that is de-asserted when the CLK input of the flip-flop in the flip-flop-based scan chain is asserted.
3 . The electronic circuit of claim 1 , wherein the memory element is an interface flip-flop with a clock input (CLK input) that is asserted when a clock input (a CLK input) of a flip-flop in the flip-flop-based scan chain is asserted, and that is de-asserted when the CLK input of the flip-flop in the flip-flop-based scan chain is de-asserted.
4 . The electronic circuit of claim 1 , wherein the latch-based scan chain includes one or more chain segments.
5 . A method to interface between a last flip-flop in a flip-flop-based part of a scan chain with a first latch in a latch-based part of the scan chain, wherein the latch-based scan chain comprises a chain of scannable latches, the method comprising:
in an interface memory element, storing a value of the last flip-flop in the flip-flop-based part of the scan chain to obtain a stored value before or at a time of asserting clock inputs of flip-flops in the flip-flop-based part of the scan chain; and
after the time of asserting the clock inputs of the flip-flops in the flip-flop-based part of the scan chain, using the stored value to set the value of the first latch in the latch-based part of the scan chain.
6 . The method of claim 5 , wherein the interface memory element is a flip-flop.
7 . The method of claim 5 , wherein the interface memory element is a latch with a flush input or a scan control input that is asserted when the clock inputs of the flip-flops are de-asserted, and that is de-asserted when the clock inputs of the flip-flops are asserted.
8 . A method to interface between a last flip-flop in a flip-flop-based part of a scan chain with a first latch in a latch-based part of the scan chain, wherein the latch-based scan chain comprises a chain of scannable latches and the first latch in the latch-based part of the scan chain is not data carrying in a functional mode, the method comprising:
before a time of first asserting a clock input of the last flip-flop in the flip-flop-based part of the scan chain, deasserting a flush input or a scan control input of the first latch in the latch-based part of the scan chain to store a value of the last flip-flop in the flip-flop-based part of the scan chain; and
before a time of second asserting the clock input of the last flip-flop in the flip-flop-based part of the scan chain, asserting and de-asserting flush inputs or scan control inputs of latches in the latch-based part of the scan chain using non-overlapping pulses to assert and de-assert the flush inputs or to assert and de-assert the scan control inputs.