Storage device for supporting dynamic allocation of memory and method of operating the same

1 . A storage device, comprising:

a plurality of memory dies;

a memory controller;

a memory information storage configured to store a defect information for each of the plurality of memory dies in which defects have occurred; and

a state detector configured to detect a memory state for each of the plurality of memory dies,

wherein the memory controller is configured to receive an externally provided operation request and to allocate required memory dies in response to the operation request,

wherein the memory controller allocates the required memory dies based on a comparison between the stored defect information of the required memory dies and the memory states of the required memory dies detected by the state detector when the memory controller receives the operation request, and

wherein the memory controller excludes from allocation memory dies with stored defect information corresponding to an environment of the detected memory states.

2 . The storage device according to claim 1 , further comprising:

an error corrector configured to correct an error in the allocated required memory dies with stored defect information corresponding to an environment other than the environment of the detected memory states.

3 . The storage device according to claim 1 , wherein the state detector comprises:

a temperature detector configured to detect a temperature of the storage device and generate temperature information based on the detected temperature; and

a voltage detector configured to detect an operating voltage applied to each of the plurality of memory dies and generate voltage information based on the detected operating voltage.

4 . The storage device according to claim 3 , wherein the defect information includes at least one of an address of a defective memory die in which a defect has occurred in a wafer test process, an address of a memory block in which the defect has occurred from among a plurality of memory blocks included in the defective memory die, an address of a page in which the defect has occurred from among a plurality of pages included in the defective memory die, and an address of defective memory cells included in the defective memory die.

5 . The storage device according to claim 4 , wherein the memory controller is configured to obtain information related to a memory die in which a defect has occurred at a temperature corresponding to the temperature information based on the defect information, and to exclude, from allocation, the memory die in which the defect has occurred at the temperature corresponding to the temperature information.

6 . The storage device according to claim 4 , wherein the memory controller is configured to obtain information related to a memory die in which a defect has occurred at a voltage corresponding to the voltage information based on the defect information, and to exclude, from allocation, the memory die in which the defect has occurred at the voltage corresponding to the voltage information.

7 . The storage device according to claim 4 , wherein the memory controller is configured to exclude, from the allocation, a memory die in which a defect has occurred at a temperature or a voltage corresponding to the temperature information or the voltage information, and to allocate a memory die having a fast operating state based on process information of memory dies, other than memory dies excluded from the allocation from among the plurality of memory dies.

8 . The storage device according to claim 1 , wherein each of the plurality of memory dies includes at least one of a volatile memory or a nonvolatile memory.

9 . The storage device according to claim 1 , wherein the memory controller is configured to, when a defect occurs in any one of the allocated required memory dies while performing an operation on the allocated required memory dies, obtain a memory state at a time at which the defect occurs from the state detector, and update the defect information based on the obtained memory state.

10 . The storage device according to claim 1 , wherein the memory controller is configured to first allocate a memory die in which no defects have occurred in a wafer test process, from among the plurality of memory dies, and subsequently allocate a memory die in which no defects have occurred in a memory state detected by the state detector.

11 . A controller, comprising:

a memory information storage configured to store defect information related to an address of a memory die in which a defect has occurred based on a result of a wafer test and a first memory condition in which the defect has occurred in the memory die;

a state detector configured to detect a current memory condition including a temperature of a storage device and an operating voltage applied to the storage device;

a memory controller configured to allocate, for an external operation request, memory dies in which no defects have occurred in the current memory condition and to exclude from allocation memory dies in which defects have occurred in the current memory condition; and

an error detector configured to perform an error correction operation on an allocated memory die in which a defect has occurred in a second memory condition different from the first memory condition, from among memory dies in which no defects have occurred in the first memory condition.

12 . The controller according to claim 11 , wherein the memory information storage comprises:

a first table configured to store information about defective memories occurring depending on a change in an operating temperature;

a second table configured to store information about defective memories occurring depending on a change in the operating voltage; and

a third table configured to store information about an operation mode of memory cells depending on changes in the operating temperature and the operating voltage.

13 . The controller according to claim 12 , wherein the memory controller is configured to allocate the memory dies based on at least one of the first table and the second table.

14 . The controller according to claim 12 , wherein the memory controller is configured to first allocate a memory die in which no defects have occurred in the wafer test, from among the memory dies, and subsequently allocate a memory die in which no defects have occurred in the current memory state detected by the state detector.

15 . A method of operating a controller, comprising:

monitoring a current operating temperature of a storage device and a current operating voltage applied to the storage device;

checking addresses of memory dies in which defects previously occurred at either the current temperature or the current voltage;

allocating memory dies for an external operation request while excluding, from allocation, memory dies in which defects previously occurred at either the current temperature or the current voltage; and

performing an error correction operation on a memory die, from among the allocated memory dies, in which a defect previously occurred at a temperature and a voltage different from the current temperature and voltage.

16 . The method according to claim 15 , wherein allocating the memory die comprises:

allocating a memory die in which no defects have occurred; and

allocating a memory die in which no defects have occurred at the current temperature and voltage.