IP Library › Granted Patent US 12682976
Granted Patent B2
US 12682976 · App. 18/592,740 · Granted Jul 14, 2026

Error detection

Inventors: Christian Alex White (Burwell, GB); Alex Beharrell (Cambridge, GB)
Assignee: Arm Limited
G11C29/18G11C2029/1806
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Quick Facts
Patent No.
US 12682976
App. No.
18/592,740
Granted
Jul 14, 2026
Kind
B2
Abstract

A data processing apparatus includes configuration circuitry that receives, from software, a set of test information and configures each of a first storage circuit and a second storage circuit to perform a consistency test based on the test information. Check circuitry performs the consistency test between data stored in the first storage circuit and the second storage circuit and updates result storage circuitry with a result of the consistency test. The result storage circuitry is accessible to the software.

Claims (57)

1 . A data processing apparatus comprising:

configuration circuitry configured to receive, from software, a set of test information and to configure each of a first storage circuit and a second storage circuit to perform a consistency test based on the test information; and

check circuitry configured to perform the consistency test between data stored in the first storage circuit and the second storage circuit and to update result storage circuitry with a result of the consistency test, wherein

the result storage circuitry is accessible to the software;

the consistency test comprises looking up an entry in the second storage circuit based on first data in the first storage circuit and comparing second data from the first storage circuit to corresponding stored data in the second storage circuit;

the first storage circuit is configured to store the first data in association with the second data such that the second data can be returned in response to queries made in respect of the first data; and

the second storage circuit is configured to store the first data in association with the second data such that the second data can be returned in response to queries made in respect of the first data.

2 . The data processing apparatus according to claim 1 , wherein

at least one of the first storage circuit and the second storage circuit is a cache.

3 . The data processing apparatus according to claim 1 , wherein

at least one of the first storage circuit and the second storage circuit is configured to cache address translations from a first domain to a second domain.

4 . The data processing apparatus according to claim 3 , wherein

the first domain is a virtual address domain; and

the second domain is a physical address domain.

5 . The data processing apparatus according to claim 1 , wherein

both of the first storage circuit and the second storage circuit are configured to cache address translations from a first domain to a second domain.

6 . The data processing apparatus according to claim 1 , wherein

the first storage circuit is smaller and faster to retrieve the data than the second storage circuit.

7 . The data processing apparatus according to claim 1 , wherein

the check circuitry comprises comparison circuitry configured to perform a comparison of the data as stored in the first storage circuit and the second storage circuit; and

the consistency test is configured to confirm that the data is the same.

8 . The data processing apparatus according to claim 7 , wherein

the consistency test is configured to compare the data in the first storage circuit against the second storage circuit.

9 . The data processing apparatus according to claim 1 , wherein

the data comprises an address; and

the consistency test is configured to check a consistency of the address.

10 . The data processing apparatus according to claim 1 , wherein

the data comprises one or more attributes; and

the consistency test is configured to check a consistency of the one or more attributes.

11 . The data processing apparatus according to claim 1 , wherein

the check circuitry is configured to perform the consistency test periodically.

12 . The data processing apparatus according to claim 1 , wherein

the check circuitry is configured to perform the consistency test for each element of the smallest of the first storage circuit and the second storage circuit.

13 . The data processing apparatus according to claim 1 , comprising:

a hierarchical memory system comprising the first storage circuit and the second storage circuit.

14 . A system comprising:

the data processing apparatus according to claim 1 , implemented in at least one packaged chip;

at least one system component; and

a board, wherein

the at least one packaged chip and the at least one system component are assembled on the board.

15 . A chip-containing product comprising the system of claim 14 wherein the system is assembled on a further board with at least one other product component.

16 . A data processing method comprising:

receiving, from software, a set of test information;

configuring each of a first storage circuit and a second storage circuit to perform a consistency test based on the test information;

performing the consistency test between data stored in the first storage circuit and the second storage circuit; and

updating result storage circuitry with a result of the consistency test, wherein

the result storage circuitry is accessible to the software;

the consistency test comprises looking up an entry in the second storage circuit based on first data in the first storage circuit and comparing second data from the first storage circuit to corresponding stored data in the second storage circuit;

the first storage circuit stores the first data in association with the second data such that the second data can be returned in response to queries made in respect of the first data; and

the second storage circuit stores the first data in association with the second data such that the second data can be returned in response to queries made in respect of the first data.

17 . A non-transitory computer-readable medium to store computer-readable code for fabrication of a data processing apparatus comprising:

configuration circuitry configured to receive, from software, a set of test information and to configure each of a first storage circuit and a second storage circuit to perform a consistency test based on the test information; and

check circuitry configured to perform the consistency test between data stored in the first storage circuit and the second storage circuit and to update result storage circuitry with a result of the consistency test, wherein

the result storage circuitry is accessible to the software;

the consistency test comprises looking up an entry in the second storage circuit based on first data in the first storage circuit and comparing second data from the first storage circuit to corresponding stored data in the second storage circuit;

the first storage circuit is configured to store the first data in association with the second data such that the second data can be returned in response to queries made in respect of the first data; and

the second storage circuit is configured to store the first data in association with the second data such that the second data can be returned in response to queries made in respect of the first data.