Memory lifecycle state sensors
Examples herein describe memory lifecycle state sensors. A memory lifecycle state sensor includes a memory and a processor. The processor is configured to write a first value to a cell of the memory at a first voltage, and the cell is storing a second value written to the cell at a second voltage that is greater than the first voltage. A value is read from the cell and compared with the first value. An indication of a lifecycle state for the cell is generated based on comparing the value with the first value, the first voltage, and the second voltage.
1 . A memory lifecycle state sensor comprising:
a memory; and
at least one processor configured to:
write a first value to a cell of the memory at a first voltage, the cell having previously stored a second value that was written to the cell at a second voltage that is greater than the first voltage;
read a value stored in the cell after writing the first value from the cell;
compare the read value with the first value; and
generate an indication of a lifecycle state for the cell based on comparing the read value with the first value, and based on a relationship between the first voltage used to write the first value and the second voltage used to write the second value.
2 . The memory lifecycle state sensor of claim 1 , wherein the at least one processor is further configured to write the second value to the cell in response to the value matching the first value.
3 . The memory lifecycle state sensor of claim 1 , wherein the first value is different from the second value.
4 . The memory lifecycle state sensor of claim 1 , wherein the value is compared with the first value using cells of an additional memory.
5 . The memory lifecycle state sensor of claim 1 , wherein the at least one processor is further configured to read the second value from the cell after the second value was written at the second voltage.
6 . The memory lifecycle state sensor of claim 1 , wherein the at least one processor is further configured to:
write the first value to an additional cell of the memory at the first voltage, the additional cell having previously stored the second value written to the additional cell at a third voltage;
read an additional value from the additional cell; and
compare the additional value with the first value.
7 . The memory lifecycle state sensor of claim 6 , wherein the third voltage is greater than the second voltage.
8 . The memory lifecycle state sensor of claim 6 , wherein the third voltage is less than the second voltage and greater than the first voltage.
9 . The memory lifecycle state sensor of claim 1 , wherein the memory includes random access memory (RAM).
10 . The memory lifecycle state sensor of claim 1 , wherein the lifecycle state is at least one of within useful life, nearing end of useful life, or end of useful life.
11 . The memory lifecycle state sensor of claim 1 , wherein the second value is written to the cell two or more times.
12 . A memory integrated circuit (IC) comprising:
a memory; and
a memory lifecycle state sensor of the memory configured to:
write reference values comprising a multi-bit pattern to a cell of the memory at a first voltage, the cell having previously stored second values written at a second voltage greater than the first voltage;
read the values stored in the cell after writing the reference values from the cell;
write test values comprising a multi-bit pattern to the cell at a third voltage that is less than the first voltage;
read test read-back values from the cell after writing the test values;
compare the test read-back values with the test values; and
generate an indication of a lifecycle state for the cell based on comparing the test read-back values with the test values, and based on a relationship between the first, second, and third voltages used to write the respective values.
13 . The memory IC of claim 12 , wherein the reference values and corresponding values of the test values are different.
14 . The memory IC of claim 12 , wherein the test read-back values are compared with the test values using cells of an additional memory.
15 . The memory IC of claim 12 , wherein the memory lifecycle state sensor is further configured to write the reference values to the cell in response to the test read-back values matching the test values.
16 . A method comprising:
writing, by at least one processor, reference values comprising a multi-bit pattern to a first cell of a memory at a first voltage;
writing, by the at least one processor, the reference values as a same multi-bit pattern to a second cell of the memory at a second voltage that is less than the first voltage;
writing, by the at least one processor, test values comprising a multi-bit pattern to the first cell and the second cell at a third voltage that is less than the second voltage;
reading, by the at least one processor, first read-back values from the first cell and second read-back values from the second cell after the test values are written;
comparing, by the at least one processor, the first read-back values and the second read-back values with the test values; and
generating, by the at least one processor, an indication of a lifecycle state for the memory based on comparing the first read-back values and the second read-back values with the test values, and based on the first, second, and third voltages used to write respective values.
17 . The method of claim 16 , wherein a value of the second read-back values does not match a corresponding value of the test values and the lifecycle state is end of useful life.
18 . The method of claim 16 , wherein the second read-back values match corresponding values of the test values and a value of the first read-back values does not match a corresponding value of the test values and the lifecycle state is nearing end of useful life.
19 . The method of claim 16 , wherein the first read-back values match corresponding values of the test values and the second read-back values match the corresponding values of the test values and the lifecycle state is within useful life.