Memory device for supporting triple adjacent error detection, memory system having the same, and operating method thereof

1 . A memory device, comprising:

a memory cell array having a plurality of memory cells connected to word lines and bit lines; and

an error correction circuit configured to perform error correction on data read from the memory cell array,

wherein the error correction circuit is configured to perform a 1-bit error correction operation, a 2-bit error detection operation, and a 3-bit error detection operation in a single unified parity check operation using a parity check matrix, and

wherein the parity check matrix is configured so that all columns of the parity check matrix are arranged in an order of odd-odd-even degree, and a leading one (LO) of each row is arranged in a stepped structure.

2 . The memory device of claim 1 , wherein

the 1-bit error correction operation includes a single error correction (SEC) operation,

the 2-bit error detection operation includes a double error detection (DED) operation, and

the 3-bit error detection operation includes a triple adjacent error detection (TAED) operation.

3 . The memory device of claim 2 , wherein

the parity check matrix includes a p×n H-matrix, and

columns of a (p−1)×n H-matrix are arranged in an odd-odd-even degree,

wherein

p is a number of rows of the p×n H-matrix, and

n is a number of columns of the p×n H-matrix.

4 . The memory device of claim 3 , wherein an i-th column (h i ) satisfies an equation h i =h i−1 +h i−3 +h i−4 .

5 . The memory device of claim 2 , wherein the parity check matrix corresponds to a SEC-DED-TAED code defining an odd column relational expression,

wherein the odd column relational expression for each odd column corresponding to an i-th column (h i ) satisfies an equation h i =h i−1 +h i−3 +h i−4 .

6 . The memory device of claim 2 , wherein the parity check matrix corresponds to a SEC-DED-TAED code based on an odd degree column.

7 . The memory device of claim 3 , wherein all the columns of the p×n H-matrix are configured in an odd degree.

8 . The memory device of claim 7 , wherein the p×n H-matrix is configured to implement double error detection (DED).

9 . The memory device of claim 1 , wherein the error correction circuit includes a systematic code and has a distributed parity.

10 . The memory device of claim 9 , wherein

p is a number of parity p-bits generated by the error correction circuit, corresponding to a number of columns of the parity check matrix, and

the systematic code includes a p×p sub-matrix having a full rank when using parity p-bits.

11 . A memory system, comprising:

at least one memory device configured to perform a first error correction operation; and

a controller configured to control the at least one memory device and to perform a second error correction operation,

wherein at least one of the first error correction operation and the second error correction operation includes performing a 1-bit error correction operation, a 2-bit error detection operation, and a 3-bit error detection operation using a parity check matrix in a single unified parity check operation, and

wherein the parity check matrix is configured so that all columns of the parity check matrix are arranged in an order of odd-odd-even degree, and leading one (LO) of each row is arranged in a stepped structure,

wherein

the 1-bit error correction operation includes a single error correction (SEC) operation,

the 2-bit error detection operation includes a double error detection (DED) operation, and

the 3-bit error detection operation includes a triple adjacent error detection (TAED) operation.

12 . The memory system of claim 11 , wherein the parity check matrix corresponds to a SEC-DED-TAED code.

13 . The memory system of claim 11 , wherein the parity check matrix corresponds to a systematic code.

14 . The memory system of claim 13 , wherein the parity check matrix is configured by replacing at least one or more column vectors to generate a diagonalized sub-matrix while maintaining a SEC-DED-TAED code.

15 . The memory system of claim 11 , wherein the parity check matrix is configured to include at least three predefined error patterns into one syndrome,

wherein the at least three predefined error patterns includes SEC, DED, and TAED.

16 . An operating method of a memory device, comprising:

encoding a message in an error correction circuit of the memory device using a parity check matrix, the encoding the message comprising performing an exclusive OR operation in a hardware-enabled XOR circuit;

receiving a codeword generated by encoding the message through a channel; and

decoding the received codeword using the parity check matrix,

wherein the parity check matrix is configured so that all columns of the parity check matrix are arranged in an order of odd-odd-even degree, and leading one (LO) of each row is arranged in a stepped structure, and

wherein the parity check matrix corresponds to a systematic SEC-DED-TAED code including a single error correction (SEC), a double error detection (DED), and a triple adjacent error detection (TAED) performed in a single unified parity check operation.

17 . The operating method of the memory device of claim 16 , wherein the parity check matrix comprises a plurality of sub-matrices, each sub-matrix of the plurality of sub-matrices each corresponding to a respective SEC-DED-TAED code according to a length of the message.

18 . The operating method of the memory device of claim 16 , further comprising:

selecting an odd weight column and two preceding columns of the parity check matrix, and

generating a syndrome for error detection based on the odd weight column and the two preceding columns selected.

19 . The operating method of the memory device of claim 16 , wherein the parity check matrix is based on at least one of expurgation, a left extension, or a right extension.