IP Library Granted Patent US 12683037
Granted Patent B2
US 12683037 · App. 18/402,123 · Granted Jul 14, 2026

Isolation barrier systems

Inventors: David Gackstetter (Rockford, IL); Robert C. Cooney (Janesville, WI)
Assignee: Hamilton Sundstrand Corporation
H01B5/002
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Quick Facts
Patent No.
US 12683037
App. No.
18/402,123
Granted
Jul 14, 2026
Kind
B2
Abstract

A system can include a chassis and a multilayer structure disposed within the chassis, the multilayer structure configured to attract and electrically isolate an arc. The multilayer structure can include one or more outer layers configured and adapted to attract the arc and an inner layer configured and adapted to electrically isolate the arc. The one or more outer layers can include a first outer layer and a second outer layer. The inner layer can be sandwiched between the first outer layer and the second outer layer.

Claims (29)

1 . A system, comprising:

a chassis; and

a multilayer structure disposed within the chassis and including (i) one or more outer layers configured to attract an arc such that the arc burns through the one or more outer layers and severs an electrical connection between the one or more outer layers and electrical ground creating an open circuit condition for the arc and (ii) an inner layer configured to electrically isolate the arc.

2 . The system of claim 1 , wherein the one or more outer layers include a first outer layer and a second outer layer, wherein the inner layer is sandwiched therebetween.

3 . The system of claim 1 , wherein the one or more outer layers are made of conductive material.

4 . The system of claim 1 , wherein the one or more outer layers have a thickness such that the arc is configured to burn through the one or more outer layers creating the open circuit condition.

5 . The system of claim 1 , wherein, in the open circuit condition, the inner layer is configured to quench the arc and shut down the system.

6 . The system of claim 5 , wherein, in the open circuit condition, the inner layer prevents the arc from traveling from a section of the chassis where the arc occurred into a neighboring section of the chassis.

7 . The system of claim 1 , wherein the chassis has an AC side and a DC side, wherein the multilayer structure is disposed between the AC side and the DC side and is configured to separate the AC side from the DC side.

8 . The system of claim 1 , wherein the chassis has a Bus A side and a Bus B side, wherein the multilayer structure is disposed between the Bus A side and the Bus B side and is configured to separate the Bus A side from the Bus B side.

9 . The system of claim 8 , wherein Bus A and Bus B are of differing potentials.

10 . The system of claim 8 , wherein Bus A and Bus B are of a same potential but connected to differing sources.

11 . The system of claim 1 , wherein the multilayer structure is configured to slide into the chassis and is configured to be bolted to a back wall of the chassis.

12 . The system of claim 1 , wherein the multilayer structure is configured to be placed between one or more printed wiring boards (PWBs).

13 . A multilayer structure, comprising:

a first outer layer;

a second outer layer, wherein the first and second outer layers are (i) configured to attract an arc and (ii) operatively connected to electrical ground such that the arc burns through one of the first and second outer layers and breaks a connection to electrical ground; and

an insulating inner layer sandwiched in between the first outer layer and the second outer layer, wherein the inner layer is configured to contain the arc.

14 . The multilayer structure of claim 13 , wherein the multilayer structure is configured to be disposed within an electronic chassis.

15 . The multilayer structure of claim 14 , wherein the multilayer structure is configured to contain the arc within a section of the electronic chassis where the arc occurs and prevent the arc from travelling into neighboring sections of the electronic chassis.

16 . The multilayer structure of claim 14 , wherein the multilayer structure is configured to slide into the electronic chassis and is configured to be bolted to a back wall of the electronic chassis.

17 . The multilayer structure of claim 14 , wherein:

the electronic chassis has an AC side and a DC side; and

the multilayer structure is configured to be disposed between the AC side and the DC side and separate the AC side from the DC side.

18 . The multilayer structure of claim 14 , wherein:

the electronic chassis has a Bus A side and a Bus B side; and

the multilayer structure is configured to be disposed between the Bus A side and the Bus B side and separate the Bus A side from the Bus B side.

19 . The multilayer structure of claim 13 , wherein the first and second outer layers are made of a conductive material.

20 . The multilayer structure of claim 13 , wherein the multilayer structure is configured to be placed between one or more printed wiring boards (PWBs).