IP Library Granted Patent US 12683046
Granted Patent B2
US 12683046 · App. 18/173,598 · Granted Jul 14, 2026

Multilayer varistor

Inventors: Yuto Akiyama (Hokkaido, JP); Ken Yanai (Hokkaido, JP); Masashi Takamura (Hokkaido, JP); Yuji Yamagishi (Hokkaido, JP); Ryosuke Usui (Hokkaido, JP)
Assignee: Panasonic Intellectual Property Management Co., Ltd.
H01C7/102H01C7/18
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Quick Facts
Patent No.
US 12683046
App. No.
18/173,598
Granted
Jul 14, 2026
Kind
B2
Abstract

A multilayer varistor according to the present disclosure includes: a sintered compact having, on a surface thereof, at least one planar portion and at least one corner portion; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the at least one planar portion and the at least one corner portion of the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes: a first high-resistivity layer covering the at least one planar portion; and a second high-resistivity layer covering the at least one corner portion. The first high-resistivity layer has a larger average thickness than the second high-resistivity layer.

Claims (32)

1 . A multilayer varistor comprising:

a sintered compact having, on a surface thereof, at least one planar portion and at least one corner portion;

an internal electrode provided inside the sintered compact;

a high-resistivity layer arranged to cover the at least one planar portion and the at least one corner portion of the sintered compact at least partially; and

an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode,

the high-resistivity layer including: a first high-resistivity layer covering the at least one planar portion; and a second high-resistivity layer covering the at least one corner portion,

the first high-resistivity layer having a larger average thickness than the second high-resistivity layer.

2 . The multilayer varistor of claim 1 , wherein

the second high-resistivity layer has an average thickness equal to or greater than 0.007 μm and equal to or less than 3.3 μm.

3 . The multilayer varistor of claim 1 , wherein

the first high-resistivity layer has an average thickness equal to or greater than 0.01 μm and equal to or less than 5 μm.

4 . The multilayer varistor of claim 1 , wherein

the first high-resistivity layer has a larger arithmetic mean surface roughness than the second high-resistivity layer.

5 . The multilayer varistor of claim 1 , wherein

the sintered compact has a pair of end faces,

the external electrode includes a pair of external electrodes arranged to respectively cover the pair of end faces of the sintered compact via the high-resistivity layer, and

a distance measured, in a direction in which the pair of end faces face each other, between the pair of external electrodes along the at least one planar portion of the sintered compact is shorter than a distance measured, in the direction in which the pair of end faces face each other, between the pair of external electrodes along the at least one corner portion of the sintered compact.

6 . A multilayer varistor comprising:

a sintered compact having, on a surface thereof, at least one planar portion and at least one corner portion;

an internal electrode provided inside the sintered compact;

a high-resistivity layer arranged to cover the at least one planar portion and the at least one corner portion of the sintered compact at least partially; and

an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode,

the high-resistivity layer including: a first high-resistivity layer covering the at least one planar portion; and a second high-resistivity layer covering the at least one corner portion,

the first high-resistivity layer having a larger arithmetic mean surface roughness than the second high-resistivity layer.

7 . The multilayer varistor of claim 6 , wherein

the second high-resistivity layer has an arithmetic mean surface roughness equal to or greater than 0.04 μm and equal to or less than 0.6 μm.

8 . The multilayer varistor of claim 6 , wherein

the first high-resistivity layer has an arithmetic mean surface roughness equal to or greater than 0.06 μm and equal to or less than 0.9 μm.

9 . The multilayer varistor of claim 6 , wherein

the sintered compact has a pair of end faces,

the external electrode includes a pair of external electrodes arranged to respectively cover the pair of end faces of the sintered compact via the high-resistivity layer, and

a distance measured, in a direction in which the pair of end faces face each other, between the pair of external electrodes along the at least one planar portion of the sintered compact is shorter than a distance measured, in the direction in which the pair of end faces face each other, between the pair of external electrodes along the at least one corner portion of the sintered compact.