IP Library Granted Patent US 12683260
Granted Patent B2
US 12683260 · App. 18/825,619 · Granted Jul 14, 2026

Antenna port termination in absence of power supply

Inventor: Sivakumar Ganesan (Austin, TX)
Assignee: PSEMI CORPORATION
H01P1/24H01Q1/50H03K17/687
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Quick Facts
Patent No.
US 12683260
App. No.
18/825,619
Granted
Jul 14, 2026
Kind
B2
Abstract

Methods and devices to address antenna termination in absence of power supplies within an electronic circuit including a termination circuit and a switching circuit. The devices include regular NMOS devices that decouple the antenna from the switching circuit in absence of power supplies while the antenna is coupled to a terminating impedance having a desired impedance value through a native NMOS device. The antenna is coupled with the switching circuit via the regular NMOS device during powered conditions while the antenna is decoupled from the terminating impedance.

Claims (27)

1 . An electronic circuit comprising:

an antenna coupled with a termination circuit and an output node; the termination circuit including a termination impedance and a first switch, the first switch comprising one or more transistors;

a control circuit configured to control the first switch to selectively connect the antenna to the termination impedance in an unpowered condition and to decouple the antenna from the termination impedance in a powered condition.

2 . The electronic circuit of claim 1 , wherein the first switch comprises native NMOS transistors.

3 . The electronic circuit of claim 2 , wherein the control circuit is configured to apply a negative bias to the first switch in the powered condition.

4 . The electronic circuit of claim 1 , further comprising a second switch positioned between the antenna and the output node, the second switch comprising regular NMOS transistors.

5 . The electronic circuit of claim 4 , wherein the second switch is configured to connect the antenna to the output node in the powered condition and to decouple the antenna from the output node in the unpowered condition.

6 . The electronic circuit of claim 5 , wherein the second switch comprises a plurality of serially connected transistors.

7 . The electronic circuit of claim 6 , wherein the first switch also comprises a plurality of serially connected transistors.

8 . The electronic circuit of claim 4 , wherein the control circuit is configured to apply a first supply voltage to the second switch in the powered condition and to remove the first supply voltage in the unpowered condition.

9 . The electronic circuit of claim 8 , wherein the control circuit applies zero bias voltage to both the first and second switches in the unpowered condition.

10 . The electronic circuit of claim 4 , wherein the second switch comprises a plurality of regular NMOS transistors configured to operate in a powered mode with positive and negative supply voltages.

11 . The electronic circuit of claim 4 , wherein the termination impedance terminates the antenna with a desired impedance in the unpowered condition.

12 . The electronic circuit of claim 11 , wherein the desired impedance is a 50-ohm impedance.

13 . The electronic circuit of claim 1 , wherein the first switch comprises a stack of three or more serially connected transistors to provide increased isolation in the unpowered condition.

14 . The electronic circuit of claim 1 , wherein the output node is connected to a plurality of single-pole single-throw (SPST) switches.

15 . The electronic circuit of claim 14 , wherein each SPST switch comprises a through switch and a shunt switch.

16 . A method for controlling termination of an antenna in an electronic circuit, comprising:

selectively coupling or decoupling the antenna to/from an output node;

providing a termination circuit with a termination impedance and a first switch;

providing a control circuit to control the first switch;

in a powered condition, maintaining the first switch in an OFF state, thereby decoupling the antenna from the termination impedance;

in an unpowered condition, switching the first switch to an ON state, thereby terminating the antenna with the termination impedance.

17 . The method of claim 16 , further comprising using native NMOS transistors in the first switch.

18 . The method of claim 17 , wherein the control circuit applies a negative voltage to the first switch in the powered condition.

19 . The method of claim 16 , further comprising providing a second switch configured to decouple the antenna from the output node in the unpowered condition.

20 . The method of claim 19 , further comprising applying a positive supply voltage to the second switch in the powered condition to couple the antenna to the output node, and applying zero-bias voltage to the first and second switches in the unpowered condition to decouple the antenna from the output node and terminate the antenna with the termination impedance.