IP Library Granted Patent US 12683297
Granted Patent B2
US 12683297 · App. 18/961,419 · Granted Jul 14, 2026

Electronic device

Inventor: Kazuyuki Hashimoto (Miaoli County, TW)
Assignee: Innolux Corporation
H01Q23/00H01Q1/22H01Q3/28
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Quick Facts
Patent No.
US 12683297
App. No.
18/961,419
Granted
Jul 14, 2026
Kind
B2
Abstract

An electronic device is provided. The electronic device includes a plurality of electronic units. Each of the plurality of electronic units includes a pixel circuit and a plurality of tunable circuits. The plurality of tunable circuits is coupled to the pixel circuit. The pixel circuit includes at least one scan transistor a plurality of de-multiplexer transistors, a plurality of bias transistors, and a storage capacitor. The plurality of de-multiplexer transistors is coupled to the at least one scan transistor. The plurality of bias transistors is coupled to the plurality of de-multiplexer transistors. The storage capacitor is coupled to a data line through the at least one scan transistor.

Claims (28)

1 . An electronic device, comprising:

a plurality of electronic units, wherein each of the plurality of electronic units comprises:

a pixel circuit; and

a plurality of tunable circuits, coupled to the pixel circuit,

wherein the pixel circuit comprises:

at least one scan transistor;

a plurality of de-multiplexer transistors, coupled to the at least one scan transistor;

a plurality of bias transistors, coupled to the plurality of de-multiplexer transistors; and

a storage capacitor, coupled to a data line through the at least one scan transistor.

2 . The electronic device according to claim 1 , wherein the pixel circuit comprises a plurality of scan transistors, and the plurality of scan transistors receive same scan signal.

3 . The electronic device according to claim 1 , wherein the plurality of de-multiplexer transistors receives different control signals, and the plurality of bias transistors receive the different control signals.

4 . The electronic device according to claim 3 , wherein a plurality of turn-on periods of the plurality of de-multiplexer transistors are non-overlapping.

5 . The electronic device according to claim 4 , wherein signal waveforms of the different control signals are complementary.

6 . The electronic device according to claim 3 , wherein one of the plurality of de-multiplexer transistors and one of the plurality of bias transistors receive a first control signal, and another of the plurality of de-multiplexer transistors and another of the plurality of bias transistors receive a second control signal.

7 . The electronic device according to claim 1 , wherein the at least one scan transistor is coupled between the data line and the plurality of de-multiplexer transistors.

8 . The electronic device according to claim 7 , wherein the pixel circuit comprises one scan transistor.

9 . The electronic device according to claim 7 , wherein the storage capacitor is coupled between the at least one scan transistor and the plurality of de-multiplexer transistors.

10 . The electronic device according to claim 7 , wherein the storage capacitor is coupled between the plurality of de-multiplexer transistors and the plurality of tunable circuits.

11 . The electronic device according to claim 1 , wherein the pixel circuit comprises a plurality of scan transistors and the plurality of de-multiplexer transistors are coupled between the data line and the plurality of scan transistors.

12 . The electronic device according to claim 11 , wherein the storage capacitor is coupled between the plurality of scan transistors and the plurality of tunable circuits.

13 . The electronic device according to claim 1 , wherein each of the plurality of bias transistors is coupled between a corresponding one of the plurality of tunable circuits and a voltage source.

14 . The electronic device according to claim 13 , wherein the storage capacitor receives a data voltage from the data line.

15 . The electronic device according to claim 14 , wherein one of the plurality of tunable circuits receives a control signal corresponding to the data voltage, and another of the plurality of tunable circuits receives a constant bias voltage from the voltage source through the corresponding one of the plurality of bias transistors.

16 . The electronic device according to claim 1 , wherein the plurality of tunable circuits is different tunable characteristics.

17 . The electronic device according to claim 16 , wherein the plurality of tunable circuits has different resonant frequency tunable ranges.

18 . The electronic device according to claim 1 , wherein each of the plurality of tunable circuits comprises a tunable component.

19 . The electronic device according to claim 18 , wherein the tunable component is a capacitance tunable component.

20 . The electronic device according to claim 1 , wherein the electronic device is an antenna device.