Distributed electrostatic discharge protection for semiconductor device

1 . A circuit comprising:

a first electrostatic discharge (ESD) protection circuit having a first terminal, a second terminal, and a first plurality of anti-parallel diodes, the first terminal of the first ESD protection circuit being coupled with a first control signal pad;

a second ESD protection circuit having a first terminal, a second terminal, and a second plurality of anti-parallel diodes, the first terminal of the second ESD protection circuit being coupled with a second control signal pad, the second terminal of the second ESD protection circuit being directly coupled with the second terminal of the first ESD protection circuit; and

a third ESD protection circuit having a first terminal and a second terminal, the first terminal of the third ESD protection circuit being coupled with one of a power supply pad or an electrical ground pad, the second terminal of the third ESD protection circuit being directly coupled with the second terminal of the first ESD protection circuit and the second terminal of the second ESD protection circuit.

2 . The circuit of claim 1 , wherein:

the third ESD protection circuit includes a third plurality of anti-parallel diodes.

3 . The circuit of claim 1 , wherein:

the first terminal of the first ESD protection circuit is coupled to a first bond pad of a semiconductor device.

4 . The circuit of claim 3 , wherein a forward-bias voltage of the first plurality of anti-parallel diodes is:

greater than one-half of a peak voltage applied between the first bond pad and a second bond pad coupled to a first terminal of the second ESD protection circuit during operation of the semiconductor device; and

greater than one-half of a peak voltage applied between the first bond pad and a third bond pad coupled to a first terminal of the third ESD protection circuit during operation of the semiconductor device.

5 . The circuit of claim 4 , wherein:

a forward-bias voltage of a second plurality of anti-parallel diodes included in the second ESD protection circuit is:

greater than one-half of a peak voltage applied between the second bond pad and the first bond pad during operation of the semiconductor device; and

greater than one-half of a peak voltage applied between the second bond pad and the third bond pad during operation of the semiconductor device; and

a forward-bias voltage of a third plurality of anti-parallel diodes included in the third ESD protection circuit is:

greater than one-half of a peak voltage applied between the third bond pad and the first bond pad during operation of the semiconductor device; and

greater than one-half of a peak voltage applied between the third bond pad and the second bond pad during operation of the semiconductor device.

6 . The circuit of claim 1 , wherein the first ESD protection circuit, the second ESD protection circuit, and the third ESD protection circuit are schematically equivalent.

7 . The circuit of claim 1 , wherein:

the first terminal of the first ESD protection circuit and the second terminal of the first ESD protection circuit are schematically equivalent;

the first terminal of the second ESD protection circuit and the second terminal of the second ESD protection circuit are schematically equivalent; and

the first terminal of the third ESD protection circuit and the second terminal of the third ESD protection circuit are schematically equivalent.

8 . The circuit of claim 1 , wherein the first ESD protection circuit includes a first plurality of reverse-mode ESD diodes.

9 . The circuit of claim 1 , wherein the power supply pad is a negative power supply pad, the circuit further comprising:

a fourth ESD protection circuit having a first terminal and a second terminal, the first terminal of the fourth ESD protection circuit being coupled with a positive power supply pad, the second terminal of the fourth ESD protection circuit being coupled with the second terminal of the first ESD protection circuit, the second terminal of the second ESD protection circuit, and the second terminal of the fourth ESD protection circuit.

10 . A semiconductor device comprising:

an active circuit;

a first bond pad coupled with the active circuit, wherein the first bond pad is a positive power supply terminal of the active circuit;

a second bond pad coupled with the active circuit, wherein the second bond pad is one of a negative power supply terminal or a ground terminal of the active circuit;

a third bond pad coupled with the active circuit, wherein the third bond pad is a signal terminal of the active circuit;

a first ESD protection circuit between and directly coupled to the first bond pad and a bridge node;

a second ESD protection circuit between and directly coupled to the second bond pad and the bridge node; and

a third ESD protection circuit between and directly coupled to the third bond pad and the bridge node.

11 . The semiconductor device of claim 10 , wherein:

the first ESD protection circuit includes a first plurality of anti-parallel diodes;

the second ESD protection circuit includes a second plurality of anti-parallel diodes; and

the third ESD protection circuit includes a third plurality of anti-parallel diodes.

12 . The semiconductor device of claim 11 , wherein a forward-bias voltage of the first plurality of anti-parallel diodes is:

greater than one-half of a peak voltage applied between the first bond pad and the second bond pad during operation of the semiconductor device; and

greater than one-half of a peak voltage applied between the first bond pad and the third bond pad during operation of the semiconductor device.

13 . The semiconductor device of claim 12 , wherein:

a forward-bias voltage of the second plurality of anti-parallel diodes is:

greater than one-half of a peak voltage applied between the second bond pad and the first bond pad during operation of the semiconductor device; and

greater than one-half of a peak voltage applied between the second bond pad and the third bond pad during operation of the semiconductor device; and

a forward-bias voltage of the third plurality of anti-parallel diodes is:

greater than one-half of a peak voltage applied between the third bond pad and the first bond pad during operation of the semiconductor device; and

greater than one-half of a peak voltage applied between the third bond pad and the second bond pad during operation of the semiconductor device.

14 . The semiconductor device of claim 10 , wherein the first ESD protection circuit, the second ESD protection circuit, and the third ESD protection circuit are schematically equivalent.

15 . The semiconductor device of claim 10 , wherein:

the first bond pad is disposed on at least a portion of the first ESD protection circuit;

the second bond pad is disposed on at least a portion of the second ESD protection circuit; and

the third bond pad is disposed on at least a portion of the third ESD protection circuit.

16 . The semiconductor device of claim 10 , further comprising:

a fourth bond pad coupled with the active circuit; and

a fourth ESD protection circuit coupled between the fourth bond pad and the bridge node,

the fourth bond pad being:

a signal terminal of the active circuit; and

disposed on at least a portion of the fourth ESD protection circuit.

17 . The semiconductor device of claim 16 , wherein the fourth ESD protection circuit includes a plurality of anti-parallel diodes.

18 . The semiconductor device of claim 17 , wherein a forward-bias voltage of the plurality of anti-parallel diodes is:

greater than one-half of a peak voltage applied between the fourth bond pad and the first bond pad during operation of the semiconductor device;

greater than one-half of a peak voltage applied between the fourth bond pad and the second bond pad during operation of the semiconductor device; and

greater than one-half of a peak voltage applied between the fourth bond pad and the third bond pad during operation of the semiconductor device.

19 . The semiconductor device of claim 10 , wherein the first ESD protection circuit includes a first plurality of reverse-mode ESD diodes.

20 . A circuit comprising:

a semiconductor substrate;

a radio frequency (RF) switch implemented in the semiconductor substrate;

an RF input bond pad disposed on the semiconductor substrate and coupled with the RF switch;

a first RF output bond pad disposed on the semiconductor substrate and coupled with the RF switch;

a second RF output bond pad disposed on the semiconductor substrate and coupled with the RF switch;

a first ESD protection circuit implemented in the semiconductor substrate, the first ESD protection circuit being between and directly coupled to the RF input bond pad and a bridge node of the circuit;

a second ESD protection circuit implemented in the semiconductor substrate, the second ESD protection circuit being between and directly coupled to the first RF output bond pad and the bridge node; and

a third ESD protection circuit implemented in the semiconductor substrate, the third ESD protection circuit being between and directly coupled to the second RF output bond pad and the bridge node.

21 . The circuit of claim 20 , wherein the semiconductor substrate includes a gallium arsenide (GaAs) substrate.

22 . The circuit of claim 20 further comprising:

a first control signal bond pad disposed on the semiconductor substrate and coupled with the RF switch;

a second control signal bond pad disposed on the semiconductor substrate and coupled with the RF switch;

an electrical ground bond pad disposed on the semiconductor substrate and coupled with the RF switch;

a fourth ESD protection circuit implemented in the semiconductor substrate, the fourth ESD protection circuit being directly coupled between the first control signal bond pad and the bridge node;

a fifth ESD protection circuit implemented in the semiconductor substrate, the fifth ESD protection circuit being directly coupled between the second control signal bond pad and the bridge node; and

a sixth ESD protection circuit implemented in the semiconductor substrate, the sixth ESD protection circuit being directly coupled between the electrical ground bond pad and the bridge node.