High anti-interference microsystem based on system in package (SIP) for power grid

1 . An anti-interference microsystem for a power grid, comprising a ceramic cavity, a ceramic substrate, a magnetic cover plate, a digital signal processing circuit, an analog signal conditioning circuit and a shield; wherein

the ceramic cavity supports the ceramic substrate, the magnetic cover plate is in sealed contact with the ceramic cavity, and the ceramic substrate is arranged in a cavity formed by the ceramic cavity and the magnetic cover plate;

a sealed shell of the anti-interference microsystem is composed of the magnetic cover plate and the ceramic cavity;

the digital signal processing circuit and the analog signal conditioning circuit are arranged on the ceramic substrate and respectively process received signals to be processed;

the shield covers an outer side of the sealed shell and configured for shielding an external magnetic field interference,

wherein the digital signal processing circuit comprises a field programmable gate array (FPGA) processor, and a double data rate (DDR), a FLASH, a CAN interface, an RS485 interface and an Ethernet card all connected with the FPGA processor, and performs sampling, storage, filtering and fast Fourier transform (FFT) processing on digital signals,

wherein the analog signal conditioning circuit comprises a low-frequency amplifier, a low-frequency analog to digital converter (ADC), a low-frequency low dropout regulator (LDO), a high-frequency amplifier, a high-frequency ADC, a high-frequency LDO and a reference source chip, and performs amplifying, filtering and an analog-to-digital conversion to analog signals, and the low-frequency ADC and the high-frequency LDO are connected with the FPGA processor,

wherein the analog signal conditioning circuit is processed through fully differential signal channels: a first channel of low frequency is taken as an example, low-frequency signals at positive and negative ends are converted into differential signals, wherein the differential signals can be received by the low-frequency ADC through a fully differential amplifier, and the digital signals converted by the low-frequency ADC are connected to the FPGA using low voltage differential signaling (LVDS) to enhance an anti-interference capacity.

2 . The anti-interference microsystem according to claim 1 , wherein

the shield comprises an inner shield arranged inside and an outer shield arranged outside;

the outer shield is a metal shield and configured for shielding a magnetic field of a low frequency band B 3 ;

the inner shield is a ferrite thin-walled shell and configured for shielding a magnetic field of an intermediate frequency band B 2 .

3 . The high-anti-interference microsystem according to claim 1 , wherein

the ceramic cavity and the ceramic substrate are sintered from ferrite ceramic materials and configured for shielding a magnetic field of a high frequency band B 1 .

4 . The high-anti-interference microsystem according to claim 1 , further comprising pins, wherein the pins are only a power supply pin, a signal input pin and a signal output pin;

the signal input pin and the signal output pin are respectively connected with the digital signal processing circuit and the analog signal conditioning circuit, the signal input pin is configured for transmitting a signal to be processed to the digital signal processing circuit and the analog signal conditioning circuit, and the signal output pin is configured for outputting the processed signal; the signal input pin and the signal output pin are led out from a position adjacent to an edge of the ceramic substrate.

5 . The high-anti-interference microsystem according to claim 1 , wherein the cavity is composed of an upper cavity located above the ceramic substrate and a lower cavity located below the ceramic substrate, the digital signal processing circuit is installed on the ceramic substrate located at a bottom of the upper cavity, and the analog signal conditioning circuit is installed on the ceramic substrate located at a top of the lower cavity.

6 . The anti-interference microsystem according to claim 1 , wherein the FPGA processor is ZYNQ 7Z020 for implementing intelligent computing, data acquisition, logic control, communication and storage.

7 . The high anti-interference microsystem according to claim 1 , wherein the FLASH selects a W25Q256 32 MB QSPI flash and supports a starting of an SD card.