IP Library Granted Patent US 12683405
Granted Patent B1
US 12683405 · App. 19/021,482 · Granted Jul 14, 2026

Proactive relay and relay driver failure identification mechanism and microgrid interconnect device including the same

Inventors: Aalokkumar Dulalchandra Datta (Kolhapur, IN); Pratik Kumar Kar (Berhampur, IN); Amit Ravindra Chavan (Kolhapur, IN)
Assignee: EATON INTELLIGENT POWER LIMITED
H02J3/388H02H1/0007H02H3/10H02J3/0012H02J3/381H02J2101/24
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Quick Facts
Patent No.
US 12683405
App. No.
19/021,482
Granted
Jul 14, 2026
Kind
B1
Abstract

A microgrid interconnect device (MID) includes: a relay structured to be connected to a utility grid and distributed energy resources (DERs); a relay driver connected to the relay and structured to actuate the relay to connect or disconnect the DERs from the grid, the relay driver further structured to provide relay state information including a relay driver fault feedback signal; a relay and relay driver failure identification mechanism connected to the relay driver and structured to perform a fault test to determine that the relay driver fault feedback signal is accurate; and a control circuit connected to the relay driver and the failure identification mechanism, the control circuit structured to cause the relay driver to actuate the relay, receive the relay state information, cause the failure identification mechanism to perform the fault test and determine that the relay driver fault feedback signal is accurate based on fault test results.

Claims (31)

1 . A microgrid interconnect device (MID), comprising:

a relay structured to be connected to a utility grid and distributed energy resources (DERs), the relay further structured to connect or disconnect the DERs from the grid;

a relay driver connected to the relay and structured to actuate the relay to connect or disconnect the DERs from the grid, the relay driver further structured to provide relay state information including a relay driver fault feedback signal;

a relay and relay driver failure identification mechanism connected to the relay driver and structured to perform a fault test to determine that the relay driver fault feedback signal is accurate; and

a control circuit connected to the relay driver and the relay and relay driver failure identification mechanism, the control circuit structured to cause the relay driver to actuate the relay, receive the relay state information, cause the relay and relay driver failure identification mechanism to perform the fault test and determine that the relay driver fault feedback signal is accurate based on fault test results.

2 . The MID of claim 1 , wherein the relay, the relay driver and the control circuit form a relay driver feedback loop and the relay state information comprises input signals to the relay driver to open or close the relay, a relay driver output voltage signal, a relay coil current signal, a fault diagnostic signal, and the relay driver fault feedback signal.

3 . The MID of claim 2 , wherein the relay and relay driver failure identification mechanism comprises:

a metal-oxide-semiconductor field-effect transistor (MOSFET) connected to the relay driver and structured to set a test overcurrent threshold, interrupt the relay driver feedback loop and inject a test fault to the relay driver;

an overcurrent limit resister connected between the relay driver and a drain of the MOSFET and structured to limit current flowing through relay driver to a coil of the relay; and

a pull-up resistor structured to pull a gate of the MOSFET high to keep the MOSFET high during normal operating conditions.

4 . The MID of claim 3 , wherein the MOSFET is an n-type MOSFET.

5 . The MID of claim 3 , wherein for a relay closing operation, the control circuit is structured to provide first and second input signals that are high to the relay driver during a first predetermined period, the relay driver output voltage is a positive pulse signal over the first predetermined period, and the relay coil current signal reaches a positive peak during the first predetermined period, and wherein for a relay opening operation, the control circuit is structured to provide the first input signal as high and the second input signal as low to the relay driver during the first predetermined period, the relay driver output voltage is a negative pulse signal over the first predetermined period, and the relay coil current signal reaches a negative peak during the first predetermined period.

6 . The MID of claim 5 , wherein during normal operation the fault diagnostic signal is a high pulse signal indicating that relay driver fault diagnostic mechanism is not activated, and the relay driver fault feedback signal is a high pulse signal indicative of no detected fault, and wherein upon detection of a fault the fault diagnostic signal is a low pulse signal indicating that the relay driver fault diagnostic mechanism is activated, and the relay driver fault feedback signal is a low pulse signal indicative of a detected fault.

7 . The MID of claim 5 , wherein the relay coil current signal having a peak equal to or higher than the test overcurrent threshold indicates that a fault has occurred.

8 . The MID of claim 6 , wherein the relay and relay driver failure identification mechanism performs the fault test by injecting a pseudo fault signal to the relay driver for a second predetermined period.

9 . The MID of claim 8 , wherein the relay and relay driver failure identification mechanism determines that the relay driver fault feedback signal is accurate based on the relay driver fault feedback signal being a low pulse signal during the second predetermined period, the low pulse signal indicative of the detected test fault.

10 . The MID of claim 8 , wherein the relay and relay driver failure identification mechanism is structured to determine a type of relay failure based on the test results.

11 . The MID of claim 10 , wherein the relay and relay driver failure identification mechanism determines that relay coils have a physical disconnect based on a determination that the relay coil current is zero.

12 . The MID of claim 10 , wherein the relay and relay driver failure identification mechanism determines that a relay short circuit protection failure has occurred based on a determination that the relay coil current touches the test overcurrent threshold and comes down to zero within a predetermined amount of time.

13 . The MID of claim 10 , wherein the relay and relay driver failure identification mechanism determines that switchover time is delayed based on a determination that the relay driver fault feedback signal during the fault test is received after the lapse of the second predetermined period.

14 . The MID of claim 10 , wherein the relay and relay driver failure identification mechanism determines that a relay gate driver circuit failure and/or a relay driver signal disconnect has occurred based on a determination that the relay coil current is zero, the relay driver output voltage is zero and the fault feedback signal is high.

15 . A relay and relay driver failure identification mechanism for use in a microgrid interconnect device (MID) having a control circuit, a relay couplable to a utility grid and distributed energy resources (DERs), a relay driver circuit structured to actuate the relay to connect or disconnect the DERs from the grid, the relay driver, the relay and the control circuit forming a relay driver feedback loop, the relay and relay driver failure identification mechanism comprising:

a metal-oxide-semiconductor field-effect transistor (MOSFET) connected to the relay driver and the control circuit, the MOSFET structured to set a test overcurrent threshold, interrupt the relay driver feedback loop and inject a test fault to the relay driver;

an overcurrent limit resister connected between the relay driver and a drain of the MOSFET and structured to limit current flowing through relay driver to a coil of the relay; and

a pull-up resistor structured to pull a gate of the MOSFET high to keep the MOSFET high during normal operating conditions,

wherein the control circuit receives relay state information including a relay driver fault feedback signal from the relay driver, cause the relay and relay driver failure identification mechanism to perform the fault test and determine that the relay driver fault feedback signal is accurate based on fault test results.

16 . The relay and relay driver failure identification mechanism of claim 15 , wherein the relay and relay driver failure identification mechanism determines that the relay driver fault feedback signal is accurate based on the relay driver fault feedback signal indicating the detected test fault.

17 . The relay and relay driver failure identification mechanism of claim 15 , wherein the relay and relay driver failure identification mechanism determines that relay coils have a physical disconnect based on a determination that relay coil current is zero.

18 . The relay and relay driver failure identification mechanism of claim 15 , wherein the relay and relay driver failure identification mechanism determines that a relay short circuit protection failure has occurred based on a determination that the relay coil current touches the test overcurrent threshold and comes down to zero within a predetermined amount of time.

19 . The relay and relay driver failure identification mechanism of claim 15 , wherein the relay and relay driver failure identification mechanism determines that switchover time is delayed based on a determination that the relay driver fault feedback signal during the fault test is received after the lapse of the second predetermined period.

20 . The relay and relay driver failure identification mechanism of claim 15 , wherein the relay and relay driver failure identification mechanism determines that a relay gate driver circuit failure and/or a relay driver signal disconnect has occurred based on a determination that the relay coil current is zero, the relay driver output voltage is zero and the fault feedback signal is high.