Multi-level structures and methods for switched-mode power supplies
Methods for modifying converter cells for switched-mode power converters, and corresponding power converter cells. The modified converter cells exhibit reduced inductance requirements, enable use of lower voltage and smaller switches, provide improved power density and efficiency, and provide for improved input/output voltage dynamic range. Embodiments of the methods generate converter cell topologies having 3 or more node voltage levels by successively applying a “split switches and connect through a capacitor” operation. The inventive processes, or variants of those processes, may be applied to converter cell topologies that are 2-level converter cells including at least one inductance and two switches, and particularly 2-level converter cells including either (1) an order of at least 3 (i.e., 3 or more energy storage elements in some combination of inductances and capacitances, but with at least one inductance) and at least 2 switches, or (2) at least 1 designed-in inductance and at least 4 switches.
1 . At least two converter cells, each of the at least two converter cells including at least 4 node voltage levels and made by modifying a 3-level converter cell that includes either (1) at least 3 designed-in energy storage elements, the at least 3 designed-in energy storage elements including one or more designed-in inductances, and at least 2 initial switches, or (2) one or more designed-in inductances and at least 4 initial switches,
wherein each of the at least two converter cells includes a first pair of replacement switches replacing a first initial switch within the 3-level converter cell and a second pair of replacement switches replacing a second initial switch within the 3-level converter cell,
wherein the first and second initial switches are not conductive at the same time during steady-state operation,
wherein a first intermediate node between the first pair of replacement switches and a second intermediate node between the second pair of replacement switches are configured to be coupled to a capacitor,
wherein each of the at least two converter cells is coupled to a common input terminal and provides an output through one output designed-in inductance of the one or more designed-in inductances, and
wherein the output of each of the at least two converter cells is coupled to a common output terminal and the designed-in inductances of at least two of the at least two converter cells are magnetically coupled with opposite poles.
2 . The at least two converter cells of claim 1 , wherein one of the first or second initial switches is a diode functioning as a switch.
3 . The at least two converter cells of claim 1 , wherein each of the at least two converter cells is a 3-level non-isolated Ćuk converter cell.
4 . The at least two converter cells of claim 1 , wherein each of the at least two converter cells is a 3-level isolated Ćuk converter cell.
5 . The at least two converter cells of claim 1 , wherein each of the at least two converter cells is a 3-level single-ended primary-inductor converter (SEPIC) converter cell.
6 . The at least two converter cells of claim 1 , wherein each of the at least two converter cells is a 3-level Zeta converter cell.
7 . The at least two converter cells of claim 1 , wherein each of the at least two converter cells is a 3-level Flyback converter cell.
8 . The at least two converter cells of claim 1 , wherein each of the at least two converter cells is a 3-level Forward converter cell.
9 . At least two converter cells, each of the at least two converter cells including at least 3 node voltage levels and made by modifying a 2-level transformer-isolated converter cell,
wherein each of the at least two converter cells includes a first pair of replacement switches replacing a first initial switch within the 2-level transformer-isolated converter cell and a second pair of replacement switches replacing a second initial switch within the 2-level transformer-isolated converter cell,
wherein the first and second initial switches are not conductive at the same time during steady-state operation,
wherein a first intermediate node between the first pair of replacement switches and a second intermediate node between the second pair of replacement switches are configured to be coupled to a capacitor,
wherein each of the at least two converter cells is coupled to a common input terminal and provides an output through a respective designed-in inductance of a plurality of designed-in inductances, and
wherein the output of each of the at least two converter cells is coupled to a common output terminal and the designed-in inductances of at least two of the at least two converter cells are magnetically coupled with opposite poles.
10 . The at least two converter cells of claim 9 , wherein one of the first or second initial switches is a diode functioning as a switch.
11 . The at least two converter cells of claim 9 , wherein each of the transformer-isolated converter cells is at least a 2-level isolated Ćuk converter cell.
12 . The at least two converter cells of claim 9 , wherein each of the transformer-isolated converter cells is at least a 2-level Flyback converter cell.
13 . The at least two converter cells of claim 9 , wherein each of the transformer-isolated converter cells is at least a 2-level Forward converter cell.
14 . At least two converter cells, each of the at least two converter cells configured to provide at least 3 node voltage levels at an output terminal,
wherein each of the at least two converter cells is coupled to a common input terminal; and
wherein the output terminal of each of the at least two converter cells is coupled to a common output terminal through a respective designed-in inductance of a plurality of designed-in inductances, and the designed-in inductances of at least two of the at least two converter cells are magnetically coupled with opposite poles.
15 . The at least two converter cells of claim 14 , wherein each of the at least two converter cells is at least a 3-level non-isolated Ćuk converter cell.
16 . The at least two converter cells of claim 14 , wherein each of the converter at least two cells is at least a 3-level isolated Ćuk converter cell.
17 . The at least two converter cells of claim 14 , wherein each of the converter at least two cells is at least a 3-level single-ended primary-inductor converter (SEPIC) converter cell.
18 . The at least two converter cells of claim 14 , wherein each of the converter at least two cells is at least a 3-level Zeta converter cell.
19 . The at least two converter cells of claim 14 , wherein each of the converter at least two cells is at least a 3-level Flyback converter cell.
20 . The at least two converter cells of claim 14 , wherein each of the converter at least two cells is at least a 3-level Forward converter cell.