Low pass filtered phase voltage to improve transient response in a buck converter
The present disclosure provides a power convertor circuit and a control circuit thereof. The power convertor circuit converts an input voltage signal to output an output voltage signal and includes a power stage circuit and a control circuit. The control circuit generates a first ripple signal according to a phase voltage signal outputted by the power stage circuit, generates a second ripple signal according to a DC signal generated by processing the first ripple signal, a reference voltage signal and a feedback signal related to the output voltage signal, and controls the power stage circuit to operate according to a preset off time when the second ripple signal continuously transcends the first ripple signal, to increase an inductor current. The control circuit calibrates the reference voltage signal by a DC offset calibration circuit, to eliminate an offset between the reference voltage signal and the feedback signal.
1 . A control circuit, applicable to a power convertor circuit, wherein the power convertor circuit comprises a power stage circuit and is configured to output an inductor current through an inductor, and the control circuit comprises:
a first ripple generation circuit, coupled to a phase output terminal of the power stage circuit, and configured to output a first ripple signal according to a phase voltage signal outputted by the power stage circuit;
a signal processing circuit, coupled to the first ripple generation circuit, and configured to process the first ripple signal to output a direct current (DC) signal;
a second ripple generation circuit, coupled to the signal processing circuit, and configured to output a second ripple signal according to the DC signal, a reference voltage signal and a feedback signal related to an output voltage signal of the power convertor circuit, wherein the second ripple generation circuit comprises:
a DC offset calibration circuit, configured to calibrate the reference voltage signal to eliminate an offset between the reference voltage signal and the feedback signal; and
a buffer circuit, coupled to the signal processing circuit, and configured to buffer the DC signal to output a buffered DC signal, wherein the buffered DC signal is related to the second ripple signal; and
a comparison circuit, coupled to the first ripple generation circuit and the buffer circuit, configured to compare the first ripple signal and the second ripple signal, and configured to trigger an on-time generation circuit to control the power stage circuit to operate according to a preset off time when the second ripple signal continuously transcends the first ripple signal, so that the inductor current is increased.
2 . The control circuit of claim 1 , wherein the first ripple generation circuit is a filter circuit, and the filter circuit is configured to filter the phase voltage signal to output the first ripple signal, and wherein the first ripple signal is related to the inductor current.
3 . The control circuit of claim 1 , wherein the first ripple generation circuit comprises:
a resistance element, comprising a first terminal coupled to the phase output terminal and a second terminal coupled to a negative input terminal of the comparison circuit; and
a capacitance element, comprising a first terminal coupled to the second terminal of the resistance element and a second terminal coupled to a ground voltage.
4 . The control circuit of claim 1 , wherein the signal processing circuit is a filter circuit, and the filter circuit is configured to filter the first ripple signal to output the DC signal, wherein the DC signal is related to a DC component of the output voltage signal.
5 . The control circuit of claim 1 , wherein the signal processing circuit comprises:
a resistance element, comprising a first terminal coupled to the first ripple generation circuit and a second terminal coupled to the second ripple generation circuit; and
a capacitance element, comprising a first terminal coupled to the second terminal of the resistance element and a second terminal coupled to a ground voltage.
6 . The control circuit of claim 1 , wherein the second ripple generation circuit further comprises:
an error amplification circuit, comprising a positive input terminal configured to receive a calibrated reference voltage signal outputted by the DC offset calibration circuit and a negative input terminal configured to receive the feedback signal, and configured to convert a difference between the calibrated reference voltage signal and the feedback signal to output an error current signal to a compensation node,
wherein the second ripple generation circuit is configured to output the second ripple signal according to the error current signal and the buffered DC signal.
7 . The control circuit of claim 6 , wherein the second ripple generation circuit further comprises:
a resistance element, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the compensation node, and the second terminal is coupled to the buffer circuit to receive the buffered DC signal outputted by the buffer circuit,
wherein the second ripple generation circuit is configured to output the second ripple signal according to the buffered DC signal and a voltage difference generated by the error current signal and the resistance element.
8 . The control circuit of claim 6 , wherein the DC offset calibration circuit is configured to calibrate the reference voltage signal according to the error current signal and a gain of the error amplification circuit, to output the calibrated reference voltage signal.
9 . The control circuit of claim 6 , wherein the DC offset calibration circuit comprises:
a resistance element, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the reference voltage signal, wherein a resistance of the resistance element is related to a gain of the error amplification circuit; and
a current mirror circuit, coupled to the first terminal of the resistance element and the error amplification circuit, and configured to duplicate the error current signal to output a duplicate current signal to the first terminal of the resistance element,
wherein the DC offset calibration circuit is configured to output the calibrated reference voltage signal at the second terminal of the resistance element by allowing the duplicate current signal to pass through the resistance element.
10 . The control circuit of claim 1 , wherein the second ripple generation circuit is coupled to the output voltage signal through a feedback circuit, and the feedback circuit is configured to output the feedback signal according to the output voltage signal.
11 . A power convertor circuit, configured to convert an input voltage signal to output an output voltage signal at a load terminal, and comprising:
a power stage circuit, configured to receive the input voltage signal, and configured to output a phase voltage signal at a phase output terminal, wherein the phase output terminal is coupled to the load terminal through an inductor; and
a control circuit, coupled to the power stage circuit, the phase output terminal and the load terminal, configured to generate a first ripple signal according to the phase voltage signal, configured to generate a second ripple signal according to a direct current (DC) signal generated by processing the first ripple signal, a reference voltage signal and a feedback signal related to the output voltage signal, and configured to control the power stage circuit to operate according to a preset off time when the second ripple signal continuously transcends the first ripple signal, so that an inductor current flowing through the inductor is increased,
wherein the control circuit comprises a DC offset calibration circuit, and the DC offset calibration circuit is configured to calibrate the reference voltage signal, to eliminate an offset between the reference voltage signal and the feedback signal,
wherein the control circuit further comprises:
a first ripple generation circuit, coupled to the phase output terminal, and configured to filter the phase voltage signal to output the first ripple signal;
a signal processing circuit, coupled to the first ripple generation circuit, and configured to process the first ripple signal to output the DC signal;
a second ripple generation circuit, coupled to the signal processing circuit, and configured to output the second ripple signal according to the DC signal, the reference voltage signal and the feedback signal, wherein the second ripple generation circuit comprises:
the DC offset calibration circuit; and
a buffer circuit, coupled to the signal processing circuit, configured to buffer the DC signal to output a buffered DC signal, wherein the buffered DC signal is related to the second ripple signal; and
a comparison circuit, coupled to the first ripple generation circuit and the second ripple generation circuit, and configured to compare the first ripple signal and the second ripple signal; and
an on-time generation circuit, coupled to the comparison circuit and the power stage circuit, and configured to be triggered by the comparison circuit to control the power stage circuit to operate according to a minimum off time when the second ripple signal continuously transcends the first ripple signal.
12 . The power convertor circuit of claim 11 , wherein the first ripple generation circuit comprises:
a resistance element, comprising a first terminal coupled to the phase output terminal and a second terminal coupled to a negative input terminal of the comparison circuit; and
a capacitance element, comprising a first terminal coupled to the second terminal of the resistance element and a second terminal coupled to a ground voltage.
13 . The power convertor circuit of claim 11 , wherein the signal processing circuit comprises:
a resistance element, comprising a first terminal coupled to the first ripple generation circuit and a second terminal coupled to the second ripple generation circuit; and
a capacitance element, comprising a first terminal coupled to the second terminal of the resistance element and a second terminal coupled to a ground voltage.
14 . The power convertor circuit of claim 11 , wherein the second ripple generation circuit further comprises:
an error amplification circuit, comprising a positive input terminal configured to receive a calibrated reference voltage signal outputted by the DC offset calibration circuit and a negative input terminal configured to receive the feedback signal, and configured to convert a difference between the calibrated reference voltage signal and the feedback signal to output an error current signal to a compensation node,
wherein the second ripple generation circuit is configured to output the second ripple signal according to the error current signal and the buffered DC signal.
15 . The power convertor circuit of claim 14 , wherein the second ripple generation circuit further comprises:
a resistance element, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the compensation node, and the second terminal is coupled to the buffer circuit to receive the buffered DC signal outputted by the buffer circuit,
wherein the second ripple generation circuit is configured to output the second ripple signal according to a voltage difference generated by the error current signal and the resistance element and the buffered DC signal.
16 . The power convertor circuit of claim 14 , wherein the DC offset calibration circuit is configured to calibrate the reference voltage signal according to the error current signal and a gain of the error amplification circuit, to output the calibrated reference voltage signal.
17 . The power convertor circuit of claim 14 , wherein the DC offset calibration circuit comprises:
a resistance element, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the reference voltage signal, wherein a resistance of the resistance element is related to a gain of the error amplification circuit; and
a current mirror circuit, coupled to the first terminal of the resistance element and the error amplification circuit, and configured to duplicate the error current signal to output a duplicate current signal to the first terminal of the resistance element,
wherein the DC offset calibration circuit is configured to output the calibrated reference voltage signal at the second terminal of the resistance element by allowing the duplicate current signal to pass through the resistance element.
18 . The power convertor circuit of claim 11 , further comprising:
a feedback circuit, coupled to the load terminal and the control circuit, and configured to output the feedback signal to the control circuit according to the output voltage signal.
19 . The power convertor circuit of claim 11 , wherein the first ripple signal is related to the inductor current, and the DC signal is related to a DC component of the output voltage signal.