Multi-level inverter

1 . An apparatus comprising:

first and second direct-current (DC) terminals;

a DC link capacitor connected between the first and the second DC terminals; and

circuitry comprising:

first, second, third and fourth switch banks each comprising a plurality of series connected switches, wherein the first switch bank is connected between a first node and a second node, the second switch bank is connected between the second node and a third node, the third switch bank is connected between the third node and a fourth node, and the fourth switch bank connected between the fourth node and a fifth node;

a first inductor connected between the first DC terminal and the second node;

a second inductor connected between the second DC terminal and the fourth node;

one or more first capacitors nested between the first and second switch banks by connecting ends of each capacitor of the one or more first capacitors between corresponding switches in each of the first and the second switch banks; and

one or more second capacitors nested between the third and fourth switch banks by connecting ends of each capacitor of the one or more second capacitors between corresponding switches in each of the third and the fourth switch banks.

2 . The apparatus of claim 1 , wherein the circuitry is configured to convert an input voltage between the first and the second DC terminals to a higher voltage between the first and the fifth nodes.

3 . The apparatus of claim 1 , wherein of the first, the second, the third and the fourth switch banks comprise low-voltage MOSFETS.

4 . The apparatus of claim 3 , wherein the low-voltage MOSFETS are 150V transistors.

5 . The apparatus of claim 1 , further comprising a processor configured to control the plurality of series connected switches of each of the first, the second, the third and the fourth switch banks to switch with a common duty cycle and at staggered times in one switching cycle.

6 . The apparatus of claim 1 , further comprising a processor configured to control:

a first switch of the plurality of series connected switches of the first switch bank and a respective first switch of the plurality of series connected switches of the fourth switch bank based on a first control input; and

a first switch of the plurality of series connected switches of the second switch bank and a respective first switch of the plurality of series connected switches of the third switch bank based on a second control input.

7 . The apparatus of claim 1 , further comprising a processor, wherein:

the plurality of series connected switches of the first switch bank, the plurality of series connected switches of the second switch bank, the plurality of series connected switches of the third switch bank, and the plurality of series connected switches of the fourth switch bank each comprise N switches; and

the processor is configured to control, at a first frequency, each switch of the plurality of series connected switches of each of the first, the second, the third and the fourth switch banks to be sequentially shifted by 1/N of a switching period of the first frequency with respect to the other switches of the plurality of series connected switches of the same switch bank.

8 . The apparatus of claim 7 , wherein the processor is configured to control:

the plurality of series connected switches of the first switch bank according to N control signals; and

the processor is configured to control the plurality of series connected switches of the second switch bank according to inverted versions of the N control signals.

9 . The apparatus of claim 8 , wherein the processor is configured to control:

the plurality of series connected switches of the third switch bank according to the N control signals; and

the processor is configured to control the plurality of series connected switches of the fourth switch bank according to inverted versions of the N control signals.

10 . The apparatus of claim 8 , wherein the processor is configured to control:

the plurality of series connected switches of the fourth switch bank according to the N control signals; and

the processor is configured to control the plurality of series connected switches of the third switch bank according to inverted versions of the N control signals.

11 . The apparatus of claim 1 , further comprising a processor configured to control at a first frequency:

each switch of the plurality of series connected switches of the first switch bank with a first duty cycle and at staggered times in one switching cycle of the first frequency;

each switch of the plurality of series connected switches of the second switch bank in a complementary to a respective switch of the plurality of series connected switches of the first switch bank; and

each switch of the plurality of series connected switches of the third switch bank with a second duty cycle and at staggered times in one switching cycle of the first frequency;

each switch of the plurality of series connected switches of the fourth switch bank in a complementary to a respective switch of the plurality of series connected switches of the third switch bank in a complementary state.

12 . The apparatus of claim 11 , wherein the second duty cycle is phase shifted 180 degrees with respect to the first duty cycle.

13 . The apparatus of claim 11 , wherein the second duty cycle is substantially the same as the first duty cycle.

14 . The apparatus of claim 1 , wherein a switch of the plurality of series connected switches of the first switch bank is configured to be switched:

simultaneously with a respective switch of the plurality of series connected switches of the fourth switch bank;

complementary to a respective switch of the plurality of series connected switches of the second switch bank; and

complementary to a respective switch of the plurality of series connected switches of the third switch bank.

15 . The apparatus of claim 1 , wherein:

N is a number of the series connected switches of the plurality of series connected switches of the first switch bank; and

each switch of the plurality of series connected switches of the first switch bank is configured to be switched at a first frequency and sequentially shifted by 1/N of a switching period of the first frequency.

16 . The apparatus of claim 1 , wherein:

each plurality of series connected switches of the first, the second, the third, and the fourth switch banks comprises two series connected switches; and

each switch of the two series connected switches is configured to be switched based on a control signal shifted by 180 degrees with respect to a control signal of the other switch of the two series connected switches.

17 . A method comprising:

switching, via a processor, first, second, third, and fourth switch banks of a boost converter to convert an input voltage between first and second direct-current (DC) input terminals to an output voltage between first and second output terminals, wherein the boost converter comprises:

a DC link capacitor connected between the first and the second DC input terminals; and

circuitry comprising:

a first inductor connected between the first DC input terminal and a second node;

a second inductor connected between the second DC input terminal and a fourth node;

the first, the second, the third and the fourth switch banks, which each comprise a plurality of series connected switches, wherein the first switch bank is connected between the first output terminal and the second node, the second switch bank is connected between the second node and a third node, the third switch bank is connected between the third node and the fourth node, and the fourth switch bank connected between the fourth node and the second output terminal;

one or more first capacitors nested between the first and second switch banks by connecting ends of each capacitor of the one or more first capacitors between corresponding switches in each of the first and the second switch banks; and

one or more second capacitors nested between the third and fourth switch banks by connecting ends of each capacitor of the one or more second capacitors between corresponding switches in each of the third and the fourth switch banks.

18 . The method of claim 17 , further comprising:

controlling, via the processor, a first switch of the plurality of series connected switches of the first switch bank and a respective first switch of the plurality of series connected switches of the third switch bank or the fourth switch bank based on a first control input; and

controlling, via the processor, a first switch of the plurality of series connected switches of the second switch bank and a respective first switch of the plurality of series connected switches of the third switch bank or the fourth switch bank based on a second control input.

19 . The method of claim 18 , wherein:

the second control input is an inverted version of the first control input.

20 . The method of claim 19 , further comprising:

controlling, via the processor, each switch of the plurality of series connected switches of the first switch bank at a first frequency; and

sequentially shifting by 1/N of a switching period of the first frequency, via the processor, switching of each of the plurality of series connected switches of the first switch bank.