IP Library › Granted Patent US 12683521
Granted Patent B2
US 12683521 · App. 18/308,342 · Granted Jul 14, 2026

Noise-lowering power FET driver

Inventors: Samir Pandit (Sivasagar, IN); Venkata Naresh Kotikelapudi (Bangalore, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H02M7/53871H02M1/088H03K17/687
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Quick Facts
Patent No.
US 12683521
App. No.
18/308,342
Granted
Jul 14, 2026
Kind
B2
Abstract

In described examples, an integrated circuit includes first and second transistors, a switch, a capacitor, a resistor, and first and second comparators. A first terminal of the switch is coupled to a first terminal of the resistor. A second terminal of the switch is coupled to a second terminal of the resistor, a first terminal of the capacitor, and a gate of the first transistor. The first comparator is configured to receive at the first input a first reference voltage, and an output of the first comparator is coupled to a gate of the second transistor. The second comparator is configured to receive at the first input a second reference voltage. A second input of the second comparator is coupled to a second input of the first comparator. An output of the second comparator is coupled to a control input of the switch.

Claims (86)

1 . An integrated circuit (IC) comprising:

a first transistor having a first terminal, a second terminal, and a control terminal;

a second transistor having a first terminal, a second terminal, and a control terminal;

a switch having a first terminal, a second terminal, and a control input;

a first comparator having first and second inputs and an output, the first comparator configured to receive a first reference voltage at the first input, wherein the output of the first comparator is coupled to the control terminal of the second transistor; and

a second comparator having first and second inputs and an output, the second comparator configured to receive a second reference voltage at the first input of the second comparator, the second input of the second comparator coupled to the second input of the first comparator, and the output of the second comparator coupled to the control input of the switch;

wherein the first comparator includes:

a third transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the third transistor coupled to the second input of the first comparator;

a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the first terminal of the third transistor, and the control terminals of the third and fourth transistors configured to receive the first reference voltage; and

a current mirror having a first terminal, a second terminal, and a ground terminal, the first terminal of the current mirror coupled to the second terminal of the fourth transistor, and the second terminal of the current mirror coupled to the output of the first comparator.

2 . An integrated circuit (IC) comprising:

a first transistor having a first terminal, a second terminal, and a control terminal;

a second transistor having a first terminal, a second terminal, and a control terminal;

a switch having a first terminal, a second terminal, and a control input;

a first comparator having first and second inputs and an output, the first comparator configured to receive a first reference voltage at the first input, wherein the output of the first comparator is coupled to the control terminal of the second transistor;

a second comparator having first and second inputs and an output, the second comparator configured to receive a second reference voltage at the first input of the second comparator, the second input of the second comparator coupled to the second input of the first comparator, and the output of the second comparator coupled to the control input of the switch; and

a low side transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the low side transistor coupled to the second inputs of the first and second comparators, the control terminal of the low side transistor coupled to the second terminals of the first and second transistors, and the first terminal of the low side transistor coupled to the first terminals of the first and second transistors.

3 . The IC of claim 2 ,

further including a ground connection;

wherein the first terminal of the low side transistor is adapted to be coupled to ground via the ground connection.

4 . The IC of claim 3 , wherein the ground connection includes an inductive connection.

5 . The IC of claim 2 , wherein the first comparator includes:

a third transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the third transistor coupled to the second input of the first comparator;

a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the first terminal of the third transistor, and the control terminals of the third and fourth transistors configured to receive the first reference voltage; and

a current mirror having a first terminal, a second terminal, and a ground terminal, the first terminal of the current mirror coupled to the second terminal of the fourth transistor, and the second terminal of the current mirror coupled to the output of the first comparator.

6 . The IC of claim 2 , wherein the low side transistor is a power field effect transistor (FET).

7 . An integrated circuit (IC) comprising:

a first transistor having a first terminal, a second terminal, and a control terminal;

a second transistor having a first terminal, a second terminal, and a control terminal;

a switch having a first terminal, a second terminal, and a control input;

a first comparator having first and second inputs and an output, the first comparator configured to receive a first reference voltage at the first input, wherein the output of the first comparator is coupled to the control terminal of the second transistor;

a second comparator having first and second inputs and an output, the second comparator configured to receive a second reference voltage at the first input of the second comparator, the second input of the second comparator coupled to the second input of the first comparator, and the output of the second comparator coupled to the control input of the switch;

an inverter having an input and an output;

a capacitor having first and second terminals;

a resistor having first and second terminals, the first terminal of the switch coupled to the first terminal of the resistor, and the second terminal of the switch coupled to the second terminal of the resistor, the first terminal of the capacitor, and the control terminal of the first transistor;

a third transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the third transistor coupled to the first terminal of the resistor and the first terminal of the switch; and

a fourth transistor including a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to a ground connection, the control terminal of the fourth transistor coupled to the control terminal of the third transistor and the output of the inverter, and the second terminal of the fourth transistor coupled to the second terminal of the resistor, the second terminal of the switch, the first terminal of the capacitor, and the control terminal of the first transistor.

8 . An integrated circuit (IC) comprising:

a turn off circuit including:

a first transistor including a first terminal, a second terminal, and a control terminal;

a second transistor including a first terminal, a second terminal, and a control terminal; and

a switch including first and second terminals; and

a low side power field-effect transistor (FET) and a high side power FET each including a first terminal, a second terminal, and a control terminal, the second terminal of the low side power FET coupled to the first terminal of the high side power FET, the control terminal of the low side power FET coupled to the second terminals of the first and second transistors, and the first terminal of the low side power FET coupled to the first terminals of the first and second transistors;

wherein the turn off circuit is configured to turn off the low side power FET by:

in a first phase, maintaining the first and second transistors in an on state and the switch in a closed state;

in a second phase after the first phase, maintaining the first and second transistors in the on state and opening the switch to an open state; and

in a third phase after the second phase, maintaining the first transistor in the on state and the switch in the open state, and turning off the second transistor to an off state.

9 . The IC of claim 8 , wherein the turn off circuit is configured to transition from operating in the first phase to operating in the second phase before a dl/dt phase of turning off the low side power FET begins, and after a voltage at the second terminal of the low side power FET starts to increase.

10 . The IC of claim 8 , wherein the turn off circuit is configured to transition from operating in the second phase to operating in the third phase before a dl/dt phase of turning off the low side power FET begins.

11 . The IC of claim 8 , wherein the switch includes a control input, and the IC further comprising:

a first comparator including a first input, a second input, and an output, the first input of the first comparator coupled to the second terminal of the low side power FET, and the output of the first comparator coupled to the control input of the switch; and

a second comparator including a first input, a second input, and an output, the first input of the second comparator coupled to the second terminal of the low side power FET, and the output of the first comparator coupled to the control terminal of the second transistor.

12 . The IC of claim 11 , wherein the second comparator is configured to receive at the second input a voltage selected in response to a slew rate of a voltage at the second terminal of the low side power FET during a dV/dt phase of turning off the low side power FET, a response rate of the second comparator, and a turn off rate of the second transistor.

13 . The IC of claim 11 , further comprising:

an inverter having an input and an output;

a capacitor having first and second terminals; and

a resistor having first and second terminals, the first terminal of the switch coupled to the first terminal of the resistor, and the second terminal of the switch coupled to the second terminal of the resistor, the first terminal of the capacitor, and the control terminal of the first transistor;

a third transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the third transistor coupled to the first terminal of the resistor and the first terminal of the switch; and

a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to a ground connection, the control terminal of the fourth transistor coupled to the control terminal of the third transistor and the output of the inverter, and the second terminal of the fourth transistor coupled to the second terminal of the resistor, the second terminal of the switch, the first terminal of the capacitor, and the control terminal of the first transistor.

14 . A system comprising:

a first transistor having a source, a drain, and a gate;

a second transistor having a source, a drain, and a gate;

a high side power field-effect transistor (FET) having a source, a drain, and a gate, the drain of the high side power FET adapted to be coupled to a voltage source;

a low side power FET having a source, a drain, and a gate, the drain of the low side power FET coupled to the source of the high side power FET, the gate of the low side power FET coupled to the drains of the first and second transistors, and the source of the low side power FET adapted to be coupled to a ground connection and the sources of the first and second transistors;

a switch having first and second terminals, and a control input;

a first comparator having first and second inputs and an output, the first comparator configured to receive at the first input a first reference voltage, and the output of the first comparator coupled to the gate of the second transistor; and

a second comparator having first and second inputs and an output, the second comparator configured to receive at the first input a second reference voltage, the second input of the second comparator coupled to the second input of the first comparator, and the output of the second comparator coupled to the control input of the switch.

15 . The system of claim 14 , wherein the high side power FET and the low side power FET are part of a DC-DC converter or an H-bridge circuit.

16 . The system of claim 14 , wherein the high side power FET is a first high side power FET and the low side power FET is a first low side power FET, and the system further comprising:

a second high side power FET having a source, a drain, and a gate; and

a second low side power FET having a source, a drain, and a gate, the drain of the second low side power FET coupled to the source of the first high side power FET.

17 . The system of claim 14 , wherein the first comparator includes:

a third transistor having a source, a drain, and a gate, the drain of the third transistor coupled to the second input of the first comparator;

a fourth transistor having a source, a drain, and a gate, the source of the fourth transistor coupled to the source of the third transistor, and the gates of the third and fourth transistors coupled to the first input of the first comparator; and

a current mirror having a first terminal, a second terminal, and a ground terminal, the first terminal of the current mirror coupled to the drain of the fourth transistor, and the second terminal of the current mirror coupled to the output of the first comparator.

18 . The system of claim 17 , further comprising a ground, wherein the source of the low side power FET is coupled to ground via the ground connection, and wherein the ground connection is an inductive connection.

19 . The system of claim 18 , further comprising:

an inverter having an input and an output;

a capacitor having first and second terminals;

a resistor having first and second terminals, the first terminal of the switch coupled to the first terminal of the resistor, and the second terminal of the switch coupled to the second terminal of the resistor, the first terminal of the capacitor, and the gate of the first transistor;

a third transistor having a source, a drain, and a gate, the drain of the third transistor coupled to the first terminal of the resistor and the first terminal of the switch; and

a fourth transistor having a source, a drain, and a gate, the source of the fourth transistor coupled to the ground connection, the gate of the fourth transistor coupled to the gate of the third transistor and the output of the inverter, and the drain of the fourth transistor coupled to the second terminal of the resistor, the second terminal of the switch, the first terminal of the capacitor, and the gate of the first transistor.

20 . The system for controlling power of claim 19 , further including a control circuit configured to:

in a first phase, maintain the first and second transistors in an on state and the switch in a closed state;

in a second phase after the first phase, maintain the first and second transistors in the on state and open the switch to an open state; and

in a third phase after the second phase, maintain the first transistor in the on state and the switch in the open state, and turn off the second transistor to an off state.