Model architecture search and optimization for hardware

1 . An apparatus comprising:

an input node to receive an input signal;

a pool of processing units to perform one or more arithmetic operations and one or more signal selection operations, wherein each of the processing units in the pool of processing units is associated with at least one parameterized model corresponding to a data transformation operation; and

a control block to configure, based on a first parameterized model, a first subset of the processing units in the pool of processing units,

wherein the first subset of the processing units processes the input signal to generate a first signal.

2 . The apparatus of claim 1 , wherein the first subset of the processing units performs at least a first signal selection operation of the one or more signal selection operations.

3 . The apparatus of claim 1 , wherein:

the first subset of the processing units comprises digital hardware blocks to process the input signal to generate the first signal; and

the control block further configures a second subset of the processing units to execute instruction codes to process the first signal to generate a second signal, wherein the processing the first signal is associated with the first parameterized model.

4 . The apparatus of claim 3 , wherein a third subset of the processing units processes the second signal to generate a third signal, and wherein the third subset of the processing units is configured based on the first parameterized model.

5 . The apparatus of claim 1 , wherein the first parameterized model for the configuration of the first subset of the processing units is trained based on:

a mapping between each of the processing units in the pool of the processing units to a different one of a plurality of differentiable building blocks; and

at least one of an input data set collected on a target hardware, an output data set collected on the target hardware, or a hardware constraint.

6 . The apparatus of claim 1 , wherein:

the input signal is associated with an input for a nonlinear electronic component;

the apparatus further comprises:

a memory to store, based on the first parameterized model, one or more lookup tables (LUTs) associated with one or more nonlinear characteristics of the nonlinear electronic component; and

a digital predistortion (DPD) block comprising the first subset of the processing units to:

select, based on the first parameterized model, first memory terms from the input signal; and

generate a pre-distorted signal based on the one or more LUTs and the selected first memory terms; and

the first signal corresponds to the pre-distorted signal.

7 . The apparatus of claim 6 , wherein:

the first subset of the processing units further selects, based on the first parameterized model, second memory terms from a feedback signal associated with an output of the nonlinear electronic component; and

the control block further configures, based on the first parameterized model, a second subset of the processing units to execute instruction codes to:

calculate DPD coefficients based on the selected second memory terms and a set of basis functions; and

update at least one of the one or more LUTs based on the calculated coefficients.

8 . The apparatus of claim 6 , wherein the control block further configures a second subset of the processing units to execute instruction codes to:

calculate DPD coefficients based on the selected first memory terms and a set of basis functions; and

update at least one of the one or more LUTs based on the calculated coefficients.

9 . An apparatus for digital predistortion (DPD), the apparatus comprising:

a pool of processing units associated with a parameterized model; and

a configuration component to select, based on the parameterized model, at least a first subset of the processing units and a second subset of the processing units in the pool of processing units,

wherein:

the first subset of the processing units transforms an input signal of a nonlinear electronic component into a pre-distorted signal based on the parameterized model and DPD coefficients; and

the second subset of the processing units updates the DPD coefficients based at least in part on a feedback signal indicative of an output of the nonlinear electronic component.

10 . The apparatus of claim 9 , wherein the first subset of the processing units transforms the input signal of the nonlinear electronic component into the pre-distorted signal by:

generating first memory terms from the input signal based on the parameterized model; and

generating the pre-distorted signal based on the first memory terms, a set of basis functions, and the DPD coefficients.

11 . The apparatus of claim 10 , wherein:

the first subset of the processing units further generates, based on the parameterized model, second memory terms from the feedback signal or the input signal; and

the second subset of the processing units updates the set of coefficients further based on the second memory terms and the set of basis functions.

12 . The apparatus of claim 9 , wherein:

the first subset of the processing units comprises one or more digital hardware blocks to transform the input signal into the pre-distorted signal; and

the second subset of the processing units comprises at least a processor to execute instruction codes to update the DPD coefficients.

13 . The apparatus of claim 9 , wherein the parameterized model comprises a plurality of differentiable functional blocks having a one-to-one correspondence to the processing units in the pool of processing units, and wherein the parameterized model is trained using a gradient descent search.

14 . A method comprising:

receiving an input signal;

configuring, based on a parameterized model associated with a data transformation, at least a first subset of processing units in a pool of processing units, wherein the first subset of processing units performs one or more signal selections and one or more arithmetic operations; and

performing the data transformation on the input signal, wherein the performing the data transformation comprises processing the input signal using the first subset of processing units to generate a first signal.

15 . The method of claim 14 , further comprising:

configuring, based on the parameterized model, a second subset of processing units in the pool of processing units,

wherein the performing the data transformation further comprises:

processing the first signal using the second subset of processing units to generate a second signal.

16 . The method of claim 15 , wherein:

the first subset of processing units comprises digital hardware blocks;

the second subset of processing units comprises one or more processors; and

the performing the data transformation comprises:

using the digital hardware blocks to process the input signal to generate the first signal; and

executing instruction codes on the one or more processors to process the first signal to generate the second signal.

17 . The method of claim 14 , wherein the parameterized model for configuring the first subset of processing units is trained based on:

a mapping between each of the processing units in the pool of processing units to a different one of a plurality of differentiable building blocks; and

at least one of an input data set collected on a target hardware, an output data set collected on the target hardware, or a hardware constraint.

18 . The method of claim 14 , wherein

the input signal is associated with an input for a nonlinear electronic component, and

wherein the processing the input signal to generate the first signal comprises:

selecting, based on the parameterized model, first memory terms from the input signal; and

generating a pre-distorted signal based on one or more lookup tables (LUTs) associated with one or more nonlinear characteristics of the nonlinear electronic component and the selected first memory terms, the first signal corresponding to the pre-distorted signal.

19 . The method of claim 18 , further comprising:

selecting, based on the parameterized model, second memory terms from a feedback signal associated with the nonlinear electronic component; and

configuring, based on the parameterized model, a second subset of processing units in the pool of processing units to execute instruction codes to:

calculate DPD coefficients based on the selected second memory terms and a set of basis functions; and

update at least one of the one or more LUTs based on the calculated coefficients.

20 . The method of claim 18 , further comprising:

configuring, based on the parameterized model, a second subset of processing units in the pool of processing units to execute instruction codes to:

calculate DPD coefficients based on the selected first memory terms and a set of basis functions; and

update at least one of the one or more LUTs based on the calculated DPD coefficients.