IP Library Granted Patent US 12683603
Granted Patent B2
US 12683603 · App. 18/826,142 · Granted Jul 14, 2026

Source follower circuit with feedback loop and self-biased diode-connected metal-oxide-semiconductor load

Inventors: Chung-Ru Wu (Taoyuan City, TW); Min-Hua Wu (Hsinchu County, TW); Yi-Keng Hsieh (Hsinchu County, TW)
Assignee: Airoha Technology Corp.
H03K17/6871H03H7/06
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Quick Facts
Patent No.
US 12683603
App. No.
18/826,142
Granted
Jul 14, 2026
Kind
B2
Abstract

A source follower circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a feedback loop circuit. Regarding the first MOS transistor, a gate terminal receives an input signal of the source follower circuit, and a source terminal outputs an output signal of the source follower circuit. Regarding the second MOS transistor, a gate terminal is coupled to a bias voltage, a source terminal is coupled to a first reference voltage, and a drain terminal is coupled to the source terminal of the first MOS transistor. Regarding the third MOS transistor, it is a self-biased diode-connected MOS transistor with its gate terminal coupled to its drain terminal. The drain terminal of the third MOS transistor is coupled to a drain terminal of the first MOS transistor, and a source terminal of the third MOS transistor is coupled to a second reference voltage.

Claims (12)

1 . A source follower circuit comprising:

a first metal-oxide-semiconductor (MOS) transistor, wherein a gate terminal of the first MOS transistor is arranged to receive an input signal of the source follower circuit, and a source terminal of the first MOS transistor is arranged to output an output signal of the source follower circuit;

a second MOS transistor, wherein a gate terminal of the second MOS transistor is coupled to a bias voltage, a source terminal of the second MOS transistor is coupled to a first reference voltage, and a drain terminal of the second MOS transistor is coupled to the source terminal of the first MOS transistor;

a third MOS transistor, wherein the third MOS transistor is a self-biased diode-connected MOS transistor, a gate terminal of the third MOS transistor is coupled to a drain terminal of the third MOS transistor, the drain terminal of the third MOS transistor is coupled to a drain terminal of the first MOS transistor, and a source terminal of the third MOS transistor is coupled to a second reference voltage;

a feedback loop circuit, coupled between the drain terminal of the first MOS transistor and the gate terminal of the second MOS transistor; and

a resistor, coupled between the drain terminal and the gate terminal of the third MOS transistor.

2 . The source follower circuit of claim 1 , further comprising:

a reference current generator circuit, coupled to the gate terminal of the third MOS transistor and arranged to generate a reference current flowing through the resistor.

3 . The source follower circuit of claim 2 , wherein each of the first MOS transistor and the second MOS transistor is a P-channel MOS transistor, the third MOS transistor is an N-channel MOS transistor, and the reference current is a source current that makes a drain voltage of the third MOS transistor lower than a gate voltage of the third MOS transistor.

4 . The source follower circuit of claim 2 , wherein the first reference voltage is higher than the second reference voltage, and the reference current is a source current that makes a drain voltage of the third MOS transistor lower than a gate voltage of the third MOS transistor.

5 . The source follower circuit of claim 1 , further comprising:

a capacitor, coupled between the gate terminal of the third MOS transistor and the second reference voltage.