High-noise-resistance and low-delay level shifting circuit for GaN half-bridge driving chip

1 . A high-noise-resistance and low-delay level shifting circuit for a GaN half-bridge driving chip, comprising: a first PMOS transistor (MP 1 ) to a fourteenth PMOS transistor (MP 14 ), a first NMOS transistor (MN 1 ) to a seventh NMOS transistor (MN 7 ), a first resistor (R 1 ), a second resistor (R 2 ), a first NLDMOS transistor (LD 1 ) to a third NLDMOS transistor (LD 3 ), and a first inverter (INV 1 ) to a fifth inverter (INV 5 ), wherein

a gate electrode of the first NLDMOS transistor (LD 1 ) and a gate electrode of the second NLDMOS transistor (LD 2 ) are respectively inputted with a low-voltage narrow-pulse signal; a source electrode of the first NLDMOS transistor (LD 1 ) and a source electrode of the second NLDMOS transistor (LD 2 ) are grounded; a drain electrode of the first NLDMOS transistor (LD 1 ) is connected to a drain electrode of the first PMOS transistor (MP 1 ), and a drain electrode of the second NLDMOS transistor (LD 2 ) is connected to a drain electrode of the seventh PMOS transistor (MP 7 ); and a gate electrode and a source electrode of the third NLDMOS transistor (LD 3 ) are grounded, and a drain electrode of the third NLDMOS transistor (LD 3 ) is connected to a drain electrode of the thirteenth PMOS transistor (MP 13 );

a gate electrode and a source electrode of the first NMOS transistor (MN 1 ) are connected to a floating ground (VSW), and a drain electrode of the first NMOS transistor (MN 1 ) is connected to the drain electrode of the first NLDMOS transistor (LD 1 ); a source electrode of the second NMOS transistor (MN 2 ) is connected to the floating ground (VSW), and a gate electrode and a drain electrode of the second NMOS transistor (MN 2 ) are shorted and connected to the floating ground (VSW) through the first resistor (R 1 ); a gate electrode of the third NMOS transistor (MN 3 ) is connected to the gate electrode of the second NMOS transistor (MN 2 ), a source electrode of the third NMOS transistor (MN 3 ) is connected to the floating ground (VSW), and a drain electrode of the third NMOS transistor (MN 3 ) is connected to a drain electrode of the eleventh PMOS transistor (MP 11 ); a gate electrode of the fourth NMOS transistor (MN 4 ) is connected to a gate electrode of the fifth NMOS transistor (MN 5 ), a source electrode of the fourth NMOS transistor (MN 4 ) is connected to the floating ground (VSW), and a drain electrode of the fourth NMOS transistor (MN 4 ) is connected to a drain electrode of the tenth PMOS transistor (MP 10 ); the gate electrode and a drain electrode of the fifth NMOS transistor (MN 5 ) are shorted and connected to the floating ground (VSW) through the second resistor (R 2 ), and a source electrode of the fifth NMOS transistor (MN 5 ) is connected to the floating ground (VSW); a gate electrode and a source electrode of the sixth NMOS transistor (MN 6 ) are connected to the floating ground (VSW), and a drain electrode of the sixth NMOS transistor (MN 6 ) is connected to the drain electrode of the second NLDMOS transistor (LD 2 ); and a gate electrode and a source electrode of the seventh NMOS transistor (MN 7 ) are connected to the floating ground (VSW), and a drain electrode of the seventh NMOS transistor (MN 7 ) is connected to the drain electrode of the third NLDMOS transistor (LD 3 );

a gate electrode and the drain electrode of the first PMOS transistor (MP 1 ) are shorted and connected to the drain electrode of the first NLDMOS transistor (LD 1 ), and a source electrode of the first PMOS transistor (MP 1 ) is connected to a floating power rail (VDDH); a gate electrode of the second PMOS transistor (MP 2 ) is connected to the gate electrode of the first PMOS transistor (MP 1 ), a source electrode of the second PMOS transistor (MP 2 ) is connected to the floating power rail (VDDH), and a drain electrode of the second PMOS transistor (MP 2 ) is connected to a source electrode of the ninth PMOS transistor (MP 9 ); a gate electrode of the third PMOS transistor (MP 3 ) is connected to the gate electrode of the first PMOS transistor (MP 1 ), a source electrode of the third PMOS transistor (MP 3 ) is connected to the floating power rail (VDDH), and a drain electrode of the third PMOS transistor (MP 3 ) is connected to a source electrode of the tenth PMOS transistor (MP 10 ); a gate electrode and a source electrode of the fourth PMOS transistor (MP 4 ) are shorted and connected to the floating power rail (VDDH), and a drain electrode of the fourth PMOS transistor (MP 4 ) is connected to the gate electrode of the first PMOS transistor (MP 1 ); a source electrode of the fifth PMOS transistor (MP 5 ) is connected to the floating power rail (VDDH), a gate electrode of the fifth PMOS transistor (MP 5 ) is connected to the drain electrode of the second NLDMOS transistor (LD 2 ), and a drain electrode of the fifth PMOS transistor (MP 5 ) is connected to a source electrode of the eleventh PMOS transistor (MP 11 ); a source electrode of the sixth PMOS transistor (MP 6 ) is connected to the floating power rail (VDDH), a gate electrode of the sixth PMOS transistor (MP 6 ) is connected to the gate electrode of the fifth PMOS transistor (MP 5 ), and a drain electrode of the sixth PMOS transistor (MP 6 ) is connected to a source electrode of the twelfth PMOS transistor (MP 12 ); a gate electrode and a drain electrode of the seventh PMOS transistor (MP 7 ) are shorted and connected to the gate electrode of the fifth PMOS transistor (MP 5 ), and a source electrode of the seventh PMOS transistor (MP 7 ) is connected to the floating power rail (VDDH); a source electrode and a gate electrode of the eighth PMOS transistor (MP 8 ) are shorted and connected to the floating power rail (VDDH), and a drain electrode of the eighth PMOS transistor (MP 8 ) is connected to the gate electrode of the fifth PMOS transistor (MP 5 ); a drain electrode of the ninth PMOS transistor (MP 9 ) is connected to the drain electrode of the second NMOS transistor (MN 2 ); a drain electrode of the twelfth PMOS transistor (MP 12 ) is connected to the drain electrode of the fifth NMOS transistor (MN 5 ); a gate electrode of the ninth PMOS transistor (MP 9 ), a gate electrode of the tenth PMOS transistor (MP 10 ), a gate electrode of the eleventh PMOS transistor (MP 11 ) and a gate electrode of the twelfth PMOS transistor (MP 12 ) are connected to an output terminal of the fifth inverter (INV 5 ); a source electrode of the thirteenth PMOS transistor (MP 13 ) is connected to the floating power rail (VDDH), and a gate electrode and the drain electrode of the thirteenth PMOS transistor (MP 13 ) are shorted and connected to the drain electrode of the third NLDMOS transistor (LD 3 ); and a gate electrode and a source electrode of the fourteenth PMOS transistor (MP 14 ) are shorted and connected to the floating power rail (VDDH), and a drain electrode of the fourteenth PMOS transistor (MP 14 ) is connected to the drain electrode of the third NLDMOS transistor (LD 3 ); and

each of the first inverter (INV 1 ), the second inverter (INV 2 ), the third inverter (INV 3 ), the fourth inverter (INV 4 ), and the fifth inverter (INV 5 ) is connected between the floating power rail (VDDH) and the floating ground (VSW); an input terminal of the first inverter (INV 1 ) is connected to the drain electrode of the third NMOS transistor (MN 3 ), and an output terminal of the first inverter (INV 1 ) is connected to the drain electrode of the fourth NMOS transistor (MN 4 ); an input terminal of the second inverter (INV 2 ) is connected to the output terminal of the first inverter (INV 1 ), and an output terminal of the second inverter (INV 2 ) is connected to the input terminal of the first inverter (INV 1 ); an input terminal of the third inverter (INV 3 ) is connected to the input terminal of the first inverter (INV 1 ), and an output terminal of the third inverter (INV 3 ) is connected to an output terminal (OUT+); and

an input terminal of the fourth inverter (INV 4 ) is connected to the output terminal of the first inverter (INV 1 ), and an output terminal of the fourth inverter (INV 4 ) is connected to an output terminal (OUT−).

2 . The high-noise-resistance and low-delay level shifting circuit according to claim 1 , wherein in a case of a positive dVSW/dt noise, a response is performed timely and the positive dVSW/dt noise is blocked by using the ninth PMOS transistor (MP 9 ), the tenth PMOS transistor (MP 10 ), the eleventh PMOS transistor (MP 11 ) and the twelfth PMOS transistor (MP 12 ) to control the circuit to operate steadily.

3 . The high-noise-resistance and low-delay level shifting circuit according to claim 2 , wherein

in the case of the positive dVSW/dt noise, the ninth PMOS transistor (MP 9 ), the tenth PMOS transistor (MP 10 ), the eleventh PMOS transistor (MP 11 ) and the twelfth PMOS transistor (MP 12 ) are turned off to prevent the positive dVSW/dt noise from being transmitted to the output terminal to control the circuit to operate steadily, wherein a noise resistance performance of the circuit is infinite in an ideal situation, depending on gate electrode-source electrode breakdown voltages and source electrode-drain electrode breakdown voltages of the first PMOS transistor (MP 1 ), the second PMOS transistor (MP 2 ), the third PMOS transistor (MP 3 ), the fifth PMOS transistor (MP 5 ), the sixth PMOS transistor (MP 6 ), the seventh PMOS transistor (MP 7 ) and the thirteenth PMOS transistor (MP 13 ) and source electrode-drain electrode breakdown voltages of the fourth PMOS transistor (MP 4 ), the eighth PMOS transistor (MP 8 ) and the fourteenth PMOS transistor (MP 14 ); and

in a case of a negative dVSW/dt noise, the second PMOS transistor (MP 2 ), the third PMOS transistor (MP 3 ), the fifth PMOS transistor (MP 5 ) and the sixth PMOS transistor (MP 6 ) are turned off, without affecting an output.