Gated level-shifter circuit
A level-shifter circuit that uses a gating signal is disclosed. The level-shifter circuit may initialize a shift node in response to a deactivation of a gating signal and an input signal. When the gating signal is activated, the level-shifter circuit may float the shift node, which can then be charged to a voltage level greater than that of an input signal. The level-shifter circuit may use the voltage level of the shift node to generate at least one output signal.
1 . An apparatus, comprising:
a half-latch circuit configured to:
initialize a shift node in response to a first determination that a gating signal and an input signal have been deactivated; and
float the shift node in response to a second determination that the gating signal has been activated; and
an input circuit configured, in response to the second determination that the gating signal has been activated and that the input signal is at a particular voltage level, to charge the shift node to a different voltage level; and
an output buffer circuit configured to generate, using the different voltage level, at least one output signal based on a voltage level of the shift node.
2 . The apparatus of claim 1 , wherein the half-latch circuit is further configured to sink a current from the shift node to initialize the shift node to voltage level of a negative supply node.
3 . The apparatus of claim 2 , wherein a rising edge of the input signal occurs subsequent to an activation of the gating signal.
4 . The apparatus of claim 2 , wherein the half-latch circuit includes a first transistor coupled between the shift node and the negative supply node, and wherein to sink the current from the shift node, the half-latch circuit is further configured to activate, using a voltage level of a control node, the first transistor.
5 . The apparatus of claim 4 , wherein the half-latch circuit further includes:
a second transistor coupled between coupled between the control node and the negative supply node, wherein the second transistor is configured to couple the control node to the negative supply node in response to the second determination that the gating signal has been activated; and
a third transistor coupled between the control node and an internal node that is further coupled to a positive supply node via a fourth transistor, wherein the third transistor is configured to decouple the control node from the internal node in response to the second determination that the gating signal has been activated.
6 . The apparatus of claim 1 , wherein the at least one output signal includes a true output signal and a complement output signal, and wherein a voltage level of the true output signal is greater than the particular voltage level.
7 . A method, comprising:
initializing, by a level-shifter circuit, a shift node to logic-low level in response to determining a gating signal and input signal have been deactivated;
floating, by the level-shifter circuit, the shift node in response to determining the gating signal has been activated;
charging, by the level-shifter circuit in response to determining an input signal is at a particular voltage level, the shift node to a different voltage level greater than the particular voltage level; and
buffering, by the level-shifter circuit, a voltage level of the shift node to generate an output signal.
8 . The method of claim 7 , wherein initializing the shift node includes sinking a current from the shift node.
9 . The method of claim 8 , wherein floating the shift node includes halting the sinking of the current from the shift node.
10 . The method of claim 8 , wherein sinking the current from the shift node includes activating, using a voltage level of a control node, at least one transistor coupled between the shift node and a negative supply node.
11 . The method of claim 10 , further comprising discharging the control node in response to determining the gating signal has been activated.
12 . The method of claim 7 , wherein charging the shift node to the different voltage level includes activating, using a complement version of the input signal, at least one transistor coupled between the shift node and a positive supply node, wherein the voltage level of the positive supply node is the same as the different voltage level.
13 . The method of claim 7 , wherein buffering the voltage level of the shift node includes generating a true version of the output signal and a complement version of the output signal, wherein a voltage level of the true version of the output signal is greater than the particular voltage level.
14 . A system, comprising:
a light-emitting diode configured, in response to receiving a predetermined current, to generate photons;
a current source configured to generate the predetermined current;
a set of switches configured to couple the current source to a positive supply node using a an analog emission signal;
a first switch configured to couple the current source to an anode of the light-emitting diode using the analog emission signal;
a second switch configured to couple a cathode of the light-emitting diode to a negative supply node using a row enable signal;
a third switch configured to couple an anode of the light-emitting diode to a pre-charge supply node using a gating signal; and
a level-shifter circuit configured to generate the analog emission signal using the gating signal and a digital emission signal.
15 . The system of claim 14 , wherein to generate the analog emission signal, the level-shifter circuit is further configured to:
initialize a shift node in response to a first determination that the gating signal and input signal have been deactivated;
float the shift node in response to a second determination that the gating signal has been activated;
charge, by the level-shifter circuit in response to a third determination that the digital emission signal is at a particular voltage level, the shift node to a voltage level of the positive supply node; and
buffer a voltage level of the shift node to generate the analog emission signal.
16 . The system of claim 15 , wherein to initialize the shift node, the level-shifter circuit is further configured to sink a given current from the shift node.
17 . The system of claim 16 , wherein to float the shift node, the level-shifter circuit is further configured to halt sinking of the given current from the shift node.
18 . The system of claim 16 , wherein to sink the given current from the shift node, the level-shifter circuit is further configured to activate, using a voltage level of a control node, at least one transistor coupled between the shift node and the negative supply node.
19 . The system of claim 18 , wherein the level-shifter circuit is further configured to discharge the control node in response to the second determination that the gating signal has been activated.
20 . The system of claim 15 , wherein to charge the shift node to the voltage level of the positive supply node, the level-shifter circuit is further configured to activate, using a complement version of the digital emission signal, at least one transistor coupled between the shift node and the positive supply node.