IP Library › Granted Patent US 12,683,614
Granted Patent B2
US 12,683,614 · App. 18/415,692 · Granted Jul 14, 2026

Clock signal noise reduction device and noise reduction method, and multi-phase delay phase-locked loop

Inventors: Yang Yang (Shanghai, CN); Xu Guo (Shanghai, CN)
Assignee: AMLOGIC (SHANGHAI) CO., LTD.
H03L7/0818H03L7/0992
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Quick Facts
Patent No.
US 12,683,614
App. No.
18/415,692
Granted
Jul 14, 2026
Kind
B2
Abstract

The present disclosure discloses a clock signal noise reduction device and noise reduction method, and a multi-phase delay phase-locked loop. The clock signal noise reduction device includes a phase generator, a phase selector, and a frequency divider. The phase generator is configured to generate a multi-phase clock signal based on an input signal. The phase selector has an input end connected with an output end of the phase generator, and is configured to select a channel of the multi-phase clock signal based on phase information and assign a delay of a preset period to a clock signal of the selected channel. The preset period is less than a cycle period of the multi-phase clock signal. The frequency divider has an input end connected to an output end of the phase selector, and is configured to perform fractional frequency division on the multi-phase clock signal delayed by the preset period.

Claims (40)

1 . A clock signal noise reduction device, comprising:

a phase generator configured to generate a multi-phase clock signal based on an input signal;

a phase selector having an input end connected with an output end of the phase generator, the phase selector being configured to select a channel of the multi-phase clock signal based on phase information and assign a delay of a preset period to a clock signal of the selected channel, wherein the preset period is less than a cycle period of the multi-phase clock signal; and

a frequency divider having an input end connected to an output end of the phase selector, the frequency divider being configured to perform fractional frequency division on the multi-phase clock signal that is delayed by the preset period to reduce a signal noise.

2 . The clock signal noise reduction device according to claim 1 , further comprising:

a phase detector connected to an output end of the frequency divider and a signal regulating end of the phase generator, and configured to obtain a phase difference between a clock signal in a current channel that has been subject to the fractional frequency division and a clock signal in an immediately previous channel that has been subject to the fractional frequency division and generate a first delay adjustment signal based on the phase difference,

wherein the phase generator is further configured to adjust the delay of the clock signal in the current channel or the clock signal in the immediately previous channel based on the first delay adjustment signal.

3 . The clock signal noise reduction device according to claim 2 , further comprising:

a phase delayer connected to the output end of the frequency divider and an input end of the phase detector, and configured to perform a delay processing on the multi-phase clock signal that has been subject to the fractional frequency division,

wherein the phase detector is connected to an output end of the phase delayer and is configured to generate a second delay adjustment signal based on the multi-phase clock signal that has been subject to the fractional frequency division and the multi-phase clock signal that has been subject to the fractional frequency division and the delay processing,

wherein the phase delayer is further configured to adjust, based on the second delay adjustment signal, a delay time length for the delay processing on the multi-phase clock signal that has been subject to the fractional frequency division.

4 . The clock signal noise reduction device according to claim 2 , wherein the phase generator is a four-phase generator, and each phase generator in the four-phase generator comprises a variable capacitor configured to adjust, based on the first delay adjustment signal, the delay of the clock signal of the phase generator where the variable capacitor is located.

5 . The clock signal noise reduction device according to claim 3 , wherein the phase generator is a four-phase generator, and each phase generator in the four-phase generator comprises a variable capacitor configured to adjust, based on the first delay adjustment signal, the delay of the clock signal of the phase generator where the variable capacitor is located.

6 . The clock signal noise reduction device according to claim 2 , wherein the phase generator is further configured to adjust a variable resistor in the phase generation circuit corresponding to the clock signal in the current channel based on the first delay adjustment signal to adjust the delay of the clock signal in the current channel, or configured to adjust a variable resistor in the phase generation circuit corresponding to the clock signal in the immediately previous channel to adjust the delay of the clock signal in the immediately previous channel.

7 . The clock signal noise reduction device according to claim 3 , wherein the phase generator is further configured to adjust a variable resistor in the phase generation circuit corresponding to the clock signal in the current channel based on the first delay adjustment signal to adjust the delay of the clock signal in the current channel, or configured to adjust a variable resistor in the phase generation circuit corresponding to the clock signal in the immediately previous channel to adjust the delay of the clock signal in the immediately previous channel.

8 . The clock signal noise reduction device according to claim 4 , wherein the phase generator is further configured to adjust a variable resistor in the phase generation circuit corresponding to the clock signal in the current channel based on the first delay adjustment signal to adjust the delay of the clock signal in the current channel, or configured to adjust a variable resistor in the phase generation circuit corresponding to the clock signal in the immediately previous channel to adjust the delay of the clock signal in the immediately previous channel.

9 . The clock signal noise reduction device according to claim 1 , wherein the preset period is 0.25 times the cycle period of the multi-phase clock signal or 0.5 times the cycle period of the multi-phase clock signal or 0.75 times the cycle period of the multi-phase clock signal.

10 . The clock signal noise reduction device according to claim 2 , wherein the preset period is 0.25 times the cycle period of the multi-phase clock signal or 0.5 times the cycle period of the multi-phase clock signal or 0.75 times the cycle period of the multi-phase clock signal.

11 . A clock signal noise reduction method, comprising:

obtaining a multi-phase clock signal;

selecting a channel of the multi-phase clock signal based on phase information and assigning a delay of a preset period to a clock signal of the selected channel, wherein the preset period is less than a cycle period of the multi-phase clock signal; and

performing fractional frequency division on the multi-phase clock signal that is delayed by the preset period to reduce a signal noise.

12 . The clock signal noise reduction method according to claim 11 , further comprising:

obtaining a phase difference between a clock signal in a current channel that has been subject to the fractional frequency division and a clock signal in an immediately previous channel that has been subject to the fractional frequency division and generating a first delay adjustment signal based on the phase difference; and

adjusting the delay of the clock signal in the current channel or the clock signal in the immediately previous channel based on the first delay adjustment signal.

13 . The clock signal noise reduction method according to claim 12 , further comprising:

performing a delay processing on the multi-phase clock signal that has been subject to the fractional frequency division;

generating a second delay adjustment signal based on the multi-phase clock signal that has been subject to the fractional frequency division and the multi-phase clock signal that has been subject to the fractional frequency division and the delay processing; and

adjusting, based on the second delay adjustment signal, a delay time length for the delay processing on the multi-phase clock signal that has been subject to the fractional frequency division.

14 . The clock signal noise reduction method according to claim 12 , wherein said adjusting the delay of the clock signal in the current channel or the clock signal in the immediately previous channel based on the first delay adjustment signal, comprising:

adjusting a variable resistor in a phase generation circuit corresponding to the clock signal in the current channel based on the first delay adjustment signal to adjust the delay of the clock signal in the current channel, or

adjusting a variable resistor in a phase generation circuit corresponding to the clock signal in the immediately previous channel to adjust the delay of the clock signal in the immediately previous channel.

15 . The clock signal noise reduction method according to claim 13 , wherein said adjusting the delay of the clock signal in the current channel or the clock signal in the immediately previous channel based on the first delay adjustment signal, comprising:

adjusting a variable resistor in a phase generation circuit corresponding to the clock signal in the current channel based on the first delay adjustment signal to adjust the delay of the clock signal in the current channel, or

adjusting a variable resistor in a phase generation circuit corresponding to the clock signal in the immediately previous channel to adjust the delay of the clock signal in the immediately previous channel.

16 . The clock signal noise reduction method according to claim 11 , wherein the preset period is 0.25 times the cycle period of the multi-phase clock signal, or 0.5 times the cycle period of the multi-phase clock signal or 0.75 times the cycle period of the multi-phase clock signal.

17 . The clock signal noise reduction method according to claim 12 , wherein the preset period is 0.25 times the cycle period of the multi-phase clock signal, or 0.5 times the cycle period of the multi-phase clock signal or 0.75 times the cycle period of the multi-phase clock signal.

18 . The clock signal noise reduction method according to claim 13 , wherein the preset period is 0.25 times the cycle period of the multi-phase clock signal, or 0.5 times the cycle period of the multi-phase clock signal or 0.75 times the cycle period of the multi-phase clock signal.

19 . The clock signal noise reduction method according to claim 14 , wherein the preset period is 0.25 times the cycle period of the multi-phase clock signal, or 0.5 times the cycle period of the multi-phase clock signal or 0.75 times the cycle period of the multi-phase clock signal.

20 . A multi-phase delay phase-locked loop, comprising the clock signal noise reduction device according to claim 1 .