Tunable digitally controlled oscillator

1 . A apparatus, comprising:

a first signal input node;

a first signal output node; and

a plurality of delay stages arranged in a first lattice, each delay stage operable to receive a signal as input and generate a delayed instance of the signal as output, wherein:

the plurality of delay stages are connected to each other in the first lattice to define a plurality of sequential ordinal paths, and each sequential ordinal path comprises a unique proper subset of the plurality of delay stages;

each sequential ordinal path subsequent to a prior sequential ordinal path includes in its unique proper subset of delay stages at least a delay stage from each prior ordinal path;

each sequential ordinal path comprises a plurality of delay stages; and

each sequential ordinal path begins at a first delay stage with an input connected to the first signal input node and ends at a second delay stage with an output connected to the first signal output node; and

wherein the plurality of delay stages is operable to receive first control data defining a selected path and the control data causes each delay stage to selectively activate or deactivate to select one of the sequential ordinal paths as the selected path for propagating an input signal received at the input of the first delay stage of the selected path to the output of the second delay stage of the selected path;

wherein the first lattice comprises a lattice of two rows and N columns of delay stages, wherein:

a first row of the two rows comprise series connected delay stages;

a second row of the two rows comprise series connected delay stages, wherein the second row is separate from the first row; and

each column of the N columns comprises at least one delay stage, and wherein an input of a delay stage of the column is connected to a node that is also connected to i) an output of a delay stage in the first row and ii) an input of a delay stage in the first row, and an output of the delay stage of the column is connected to i) a node that is also connected to an output of a delay stage in the second row and ii) an input of a delay stage in the second row; and

each delay stage comprises a plurality of delay elements that may be individually enabled, and for each delay stage a delay for the stage is proportional to a number of the plurality of delay elements are enabled; and

each delay stage is operable to receive second control data defining delay stage adjustments for each delay stage in a selected path to adjust an overall time delay for propagating an input signal received at the first delay stage to the output of the second delay stage.

2 . The apparatus of claim 1 , wherein:

the plurality of delay stages are further connected to each other in the first lattice to define an initial ordinal path that is prior to each of the sequential ordinal paths;

the initial ordinal path begins at a third delay with an input connected to the first signal input node, and the third delay stage is different from the first delay stage;

the first control data can further define the initial ordinal path as the selected path and the control data causes each delay stage to selectively activate or deactivate to select the selected path for propagating an input signal received at the third delay stage.

3 . The apparatus of claim 2 , wherein the initial ordinal path ends at the second delay stage with the output connected to the first signal output node.

4 . The apparatus of claim 2 , wherein the initial ordinal path ends at an output of the third delay stage with the output of the third delay stage connected to the first signal output node.

5 . The apparatus of claim 1 , further comprising:

a feedback circuit that receives the delayed instance of the input signal output at the first signal output node and, in response, generates an input signal that is applied to the first signal input node.

6 . The apparatus of claim 5 , wherein the feedback circuit comprises a two-input NAND gate, a first input coupled to the first signal output node, and a second input coupled to an enable signal, and an output coupled to the first signal input node.

7 . The apparatus of claim 1 , further comprising:

a second signal input node;

a second signal output node; and

a plurality of delay stages arranged in a second lattice, each delay stage operable to receive a signal as input and generate a delayed instance of the signal as output, wherein:

the plurality of delay stages are connected to each other in the second lattice to define a plurality of sequential ordinal paths, and each sequential ordinal path comprises a unique proper subset of the plurality of delay stages;

each sequential ordinal path subsequent to a prior sequential ordinal path includes in its unique proper subset of delay stages at least a delay stage from each prior ordinal path;

each sequential ordinal path comprises a plurality of delay stages; and

each sequential ordinal path begins at a fourth delay stage with an input connected to the second signal input node and ends at a fifth delay stage with an output connected to the second signal output node; and

the plurality of delay stages is operable to receive third control data defining a selected path and the control data causes each delay stage to selectively activate or deactivate to select one of the sequential ordinal paths as the selected path for propagating an input signal received at the input of the fourth delay stage of the selected path to the output of the fifth delay stage of the selected path;

wherein:

the first signal input node is connected to an input signal;

the first signal output node is connected to the second signal input node; and

the second signal output node provides an output signal of the apparatus.

8 . The apparatus of claim 7 , wherein the plurality of delay stages in the first lattice has a voltage sensitivity that is different from a voltage sensitivity of the plurality of delay stages in the second lattice.

9 . The apparatus of claim 1 , wherein each delay stage comprises a plurality of tri-state inverters connected in parallel.

10 . The apparatus of claim 7 , further comprising:

a feedback circuit that receives the delayed instance of the input signal output at the second signal output node and, in response, generates an input signal that is applied to the first signal input node.

11 . A method implemented in an electronic device, comprising:

determining first control data for a plurality of delay stages arranged in a first lattice, wherein:

each delay stage is operable to receive a signal as input and generate a delayed instance of the signal as output;

the plurality of delay stages are connected to each other in the first lattice to define a plurality of sequential ordinal paths, and each sequential ordinal path comprises a unique proper subset of the plurality of delay stages;

each sequential ordinal path subsequent to a prior sequential ordinal path includes in its unique proper subset of delay stages at least a delay stage from each prior ordinal path;

each sequential ordinal path comprises a plurality of delay stages; and

each sequential ordinal path begins at a first delay stage with an input connected to the first signal input node and ends at a second delay stage with an output connected to the first signal output node; and

the first control data defines a selected path and causes each delay stage to selectively activate or deactivate to select one of the sequential ordinal paths as the selected path for propagating an input signal received at the input of the first delay stage of the selected path to the output of the second delay stage of the selected path;

applying the first control data to the plurality of delay stages; and

applying an input signal to the first signal input node to generate a delayed instance of the input signal at the first signal output node;

wherein:

the first lattice comprises a lattice of two rows and N columns of delay stages, wherein:

a first row of the two rows comprise series connected delay stages;

a second row of the two rows comprise series connected delay stages, wherein the second row is separate from the first row; and

each column of the N columns comprises at least one delay stage, and wherein an input of a delay stage of the column is connected to a node that is also connected to i) an output of a delay stage in the first row and ii) an input of a delay stage in the first row, and an output of the delay stage of the column is connected to i) a node that is also connected to an output of a delay stage in the second row and ii) an input of a delay stage in the second row; and

each delay stage comprises a plurality of delay elements that may be individually enabled, and for each delay stage a delay for the stage is proportional to a number of the plurality of delay elements are enabled; and

determining second control data defining delay stage adjustments for each delay stage in a selected path to adjust an overall time delay for propagating an input signal received at the first delay stage to the output of the second delay stage; and

applying the second control data to the plurality of delay stages.

12 . The method of claim 11 , wherein:

the plurality of delay stages are further connected to each other in the first lattice to define an initial ordinal path that is prior to each of the sequential ordinal paths;

the initial ordinal path begins at a third delay with an input connected to the first signal input node, and the third delay stage is different from the first delay stage;

the first control data can further define the initial ordinal path as the selected path and the control data causes each delay stage to selectively activate or deactivate to select the selected path for propagating an input signal received at the third delay stage.

13 . The method of claim 11 , further comprising:

generating a feedback signal from the delayed instance of the input signal output at the first signal output node; and

providing the feedback signal as the input signal to the first signal input node.

14 . The method of claim 11 , further comprising:

determining second control data to define delay stage adjustments for each delay stage in a selected path to adjust an overall time delay for propagating an input signal received at the first delay stage of the selected path to the last delay stage of the selected path; and

applying the second control data to the delay stages in the selected path.

15 . The method of claim 11 , further comprising:

cascading a plurality of delay stages arranged in a second lattice to the plurality of delay stages arranged in the first lattice by connecting the first signal output node of the first lattice to a second signal input node of the second lattice; and

determining second control data for the plurality of delay stages arranged in the second lattice, wherein the second control data defines a selected path and causes each delay stage to selectively activate or deactivate to select one of a plurality of sequential ordinal paths as the selected path for propagating the input signal received at the first delay stage of the selected path to the last delay stage of the selected path.

16 . The method of claim 15 , wherein the plurality of delay stages in the first lattice has a voltage sensitivity that is different from a voltage sensitivity of the plurality of delay stages in the second lattice.

17 . The method of claim 15 , wherein each delay stage comprises a plurality of tri-state inverters connected in parallel.