Charge-steering-sampling phase discriminator, digital loop filter and charge-steering-sampling all digital phase-locked loop thereof

1 . A Charge-Steering-Sampling Phase Discriminator (CSS-PD), with two input signals (V ref1 ) and (V ref2 ) and an output signal (Dout), input signals (V ref1 ) and (V ref2 ) being a pair of sinusoidal differential signals, the CSS-PD comprises:

a Frac-N C-DAC, comprising a capacitors array (C frac ) and a first two-way switches array correspondingly; a up-plate defined by a connection formed of ends of one half of capacitors of the capacitors array (C frac ), a baseplate defined by another connection formed of ends of the other half of capacitors of the capacitors array (C frac ), and the other ends of all capacitors of the capacitors array (C frac ) connected with one corresponding first two-way switch respectively in order to receive a reference voltage (V ref,adc ) or receive a low-level voltage (V SS ); the first two-way switches array under control of timing-control signals (clk_frac);

a CSS, comprising two first switches (S 1 ) under the control of timing-control signals (clk_div) about a fractional frequency, two second switches (S 2 ) under the control of timing-control signals (clk_css) about a trigger sampling pulse, and two transistors (M 1 ) and (M 2 ); timing-control signals (clk_css) activated when the falling edge of timing-control signals (clk_div) arrived; the two bases of transistors (M 1 ) and (M 2 ) receiving input signals (V ref1 ) and (V ref2 ) respectively; the two emitters of transistors (M 1 ) and (M 2 ) both receiving low-level voltage (V SS ); the collector of transistor (M 1 ) in turn connected with one first switch (S 1 ) and one second switch (S 2 ) in order to receive a high-level voltage V DD ), and the collector of transistor (M 2 ) in turn connected with another first switch (S 1 ) and another second switch (S 2 ) in order to receive high-level voltage (V DD );

a SAR-ADC, comprising a capacitors array (C sar ) and a second two-way switches array correspondingly; another up-plate defined by a connection formed of ends of one half of capacitors of the capacitors array (C sar ), another baseplate defined by another connection formed of ends of the other half of capacitors of the capacitors array (C sar ), and the other ends of all capacitors of the capacitors array (C sar ) connected with one corresponding second two-way switch respectively in order to receive reference voltage (V ref,adc ) or receive low-level voltage (V SS ); the second two-way switches array under control of timing-control signals (clk_sar); the Frac-N C-DAC reset when the rising edge of the timing-control signal (clk_sar) arrived; the two up-plates both connected with the collector of transistor (M 1 ), and the two baseplates both connected with the collector of transistor (M 2 );

wherein output signal (Dout) is defined by the output signal (N frac ) between the up-plate and the baseplate of the SAR-ADC; signal (D frac ) is defined by the output signal between the up-plate and the baseplate of the Frac-N C-DAC, then is also the input signal (N int ) of the SAR-ADC; the CSS-PD has a controlling method comprising:

(1) charge presetting

when timing-control signals (clk_div) was on the high level voltage, the two up-plates were charged to high-level voltage (V DD ) by switching on S 1 under the control of timing-control signals (clk_div), and the two baseplates were set on low-level voltage (V SS ) by switching on the two two-way switches arrays under the control of timing-control signals (clk_frac) and timing-control signals (clk_sar) respectively;

(2) charge-steering sampling

when the falling edge of timing-control signals (clk_div) was arrived and timing-control signals (clk_css) was activated, a phase difference (ΔV err,pn ) defined by the phase difference between timing-control signals (clk_div) and the two input signals (V ref1 ) and (V ref2 ) was detected by switching on the second switch (S 2 ) under the control of timing-control signals (clk_css);

(3) fractional charge compensating

when phase difference (ΔV err,pn ) included two errors (ΔV err,pn ) and ΔV err,frac , error (ΔV err,pn ) defined by PN and error (ΔV err,frac ) defined by a periodic error between the two adjacent periods of input signals (V ref1 ) and (V ref2 ), error (ΔV err,frac ) had fractional charge compensating by setting part of the capacitors of the capacitors array (C frac ) to reference voltage (V ref,adc ) because that part of two-way switches of the first two-way switches array were switched on respectively under the control of timing-control signals (clk_frac); reference voltage (V ref,adc ) was satisfied the following formula: ΔV err,frac =D frac ·C unit /(C frac +C sar )·V ref,adc ; in the formula, C unit is for capacitance of capacitors array (C frac ), C frac is also for capacitance of capacitors array (C frac ), C sar is also for capacitance of capacitors array (C sar );

(4) digitalizing

phase difference (ΔV err,pn ) was digitalized by the SAR-ADC, and the output signal (Dout) was output accordingly.

2 . The CSS-PD according to claim 1 , wherein input signals (V ref1 ) and (V ref2 ) were generated by a on-chip Sinusoidal signal generator; the generator includes a off-chip high Q-value resonator and a on-chip amplifier; a same end and a reverse end of the amplifier are respectively and electrically connected to the two ends of the resonator, input signals (V ref1 ) and (V ref2 ) are output by the two output ends of the amplifier.

3 . The CSS-PD according to claim 1 , wherein the fractional frequency is generated by an oscillator.

4 . The CSS-PD according to claim 3 , wherein timing-control signals (clk_frac) is defined by delaying timing-control signals (clk_div).

5 . The CSS-PD according to claim 4 , wherein timing-control signals (clk_sar) is defined by delaying timing-control signals (clk_frac).

6 . A Digital Loop Filter DLF, comprises:

a proportional path (γ), for receiving the output signal (Dout) of the CSS-PD according to claim 1 ;

an integral path (ρ), for receiving output signal (Dout), too;

a first accumulator, for accumulating two output signals of (γ) and (ρ).

7 . The DLF according to claim 6 , further comprises:

a DZ, front of ρ to receive output signal (Dout).

8 . The DLF according to claim 7 , further comprises:

a MRE, front of (γ) and the DZ to receive output signal (Dout) and output a signal (D err ) both to (γ) and the DZ.

9 . The DLF according to claim 8 , wherein (γ) is a first shifter used for shifting signal (D err ).

10 . The DLF according to claim 9 , wherein (ρ) comprises:

a second shifter;

a second accumulator, used to accumulate the two output signals of the DZ and the second shifter; the second shifter used to receive the output signal of the second accumulator;

an integrator e, used to receive the output signal of the second shifter and output a signal to the first accumulator.

11 . A Charge-Steering-Sampling All Digital Phase-Locked Loop CSS-ADPLL, comprises:

the CSS-PD, according to claim 1 ;

a DLF, used to digital filter (Dout) of the CSS-PD, the DLF comprises:

a proportional path (γ), for receiving the output signal (Dout) of the CSS-PD;

an integral path (ρ), for receiving the output signal (Dout), too;

a first accumulator, for accumulating two output signals of (γ) and (ρ);

a DZ, front of ρ to receive digital filter (Dout); and

a MRE, front of (γ) and the DZ to receive the output signal (Dout) and output a signal (D err ) both to (γ) and the DZ;

a DCO, used to numerically control the output signal of the DLF;

a CML2 divider, being a CML fixed frequency divider used to turn the output signal of the DCO into a preliminary frequency-division signal;

a LMS, used to process signal (D frac ) and signal (D err ) according to the Least-Mean-Square;

a Σ, used to convert an analog signal to a digital signal, the output signal of the LMS being the analog signal;

a third accumulator, used to accumulate output signal (N frac ) and the output signal of the Σ;

a DSM, used to modulate output signal (N frac );

a fourth accumulator, used to accumulate input signal (N int ) and two output signals of the third accumulator and the DSM;

a MMDIV, used for underclocking the preliminary frequency-division signal and the output signal of the fourth accumulator to timing-control signals (clk_div).

12 . The CSS-ADPLL according to claim 11 , wherein input signals (V ref1 ) and (V ref2 ) were generated by a on-chip Sinusoidal signal generator; the generator includes a off-chip high Q-value resonator and a on-chip amplifier; a same end and a reverse end of the amplifier are respectively and electrically connected to the two ends of the resonator, input signals (V ref1 ) and (V ref2 ) are output by the two output ends of the amplifier.

13 . The CSS-ADPLL according to claim 11 , wherein the fractional frequency is generated by an o oscillator.

14 . The CSS-ADPLL according to claim 13 , wherein timing-control signals (clk_frac) is defined by delaying timing-control signals (clk_div).

15 . The CSS-ADPLL according to claim 14 , wherein timing-control signals (clk_sar) is defined by delaying timing-control signals (clk_frac).

16 . The CSS-ADPLL according to claim 11 , wherein (γ) is a first shifter used for shifting signal (D err ).

17 . The CSS-ADPLL according to claim 11 , wherein (ρ) comprises:

a second shifter;

a second accumulator, used to accumulate the two output signals of the DZ and the second shifter; the second shifter used to receive the output signal of the second accumulator;

an integrator e, used to receive the output signal of the second shifter and output a signal to the first accumulator.