Current steering digital-to-analog converter with reduced inter-cell interference
A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.
1 . A DAC cell circuit comprising:
at least a DAC cell, comprising:
a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage;
a capacitor coupled between the gate and the drain of the first MOSFET; and
a dead-band switch coupled between the gate of the first MOSFET and the bias node;
wherein the dead-band switch is open during a data transition.
2 . The DAC cell circuit of claim 1 , comprising:
a plurality of DAC cells coupled in parallel;
a voltage generating circuit coupled to the first current and the second current for generating a differential output voltage; and
a reference voltage coupled to the source of the first MOSFET of each DAC cell.
3 . The DAC cell circuit of claim 2 , wherein the dead-band switches are controlled by a signal which is periodic with respect to a frequency which is equal to an input data rate of the plurality of DAC cells.
4 . The DAC cell circuit of claim 3 , further comprising:
a common mode voltage; and
a plurality of switches coupled between the common mode voltage and the drain of the first MOSFET of each DAC cell.
5 . The DAC cell circuit of claim 4 , wherein each DAC cell comprises a second MOSFET coupled in cascode above the first MOSFET, and the DAC cell circuit further comprises a cascode voltage coupled to the gate of the second cascode MOSFET of each DAC cell.
6 . The DAC cell circuit of claim 4 , wherein each DAC cell comprises a second MOSFET coupled in cascode below the first MOSFET, and the DAC cell circuit further comprises a second bias voltage coupled to a gate of the second cascode MOSFET of each DAC cell.
7 . The DAC cell circuit of claim 6 , wherein each DAC cell further comprises a second dead-band switch coupled between the second bias voltage and the gate of the second MOSFET.
8 . The DAC cell circuit of claim 4 , wherein each DAC cell comprises a resistor coupled between the source of the first MOSFET and the reference voltage.
9 . A complementary DAC cell circuit comprising two DAC cell circuits of claim 4 , coupled together in a mirrored architecture.
10 . The complementary DAC cell circuit of claim 9 , further comprising differential dead-band switches coupled between the differential output voltage and the common mode voltages.
11 . The DAC cell circuit of claim 1 , wherein the MOSFET is a PMOS.
12 . The DAC cell circuit of claim 1 , wherein the transistor is an NMOS.
13 . The DAC cell circuit of claim 1 , wherein the MOSFET is an NPN transistor.
14 . The DAC cell circuit of claim 1 , wherein the MOSFET is a PNP transistor.