Driver circuit
A single ended driver circuit ( 100 ) for a digital to analog conversion, DAC, cell is presented. The driver circuit ( 100 ) comprises one positive single-edge latch ( 200 ) configured to provide a positive edge latched data signal (S + ) by latching a positive edge of a data signal (D) synchronized by a first clock signal (CLK 1 ), and a negative single-edge latch ( 300 ) configured to provide a negative edge latched data signal (S − ) by latching a negative edge of the data signal (D) synchronized by a second clock signal (CLK 2 ). The positive edge latched data signal (S + ) and the negative edge latched data signal (S − ) are combined to provide a drive signal (S) having a positive edge synchronized by the first clock signal (CLK 1 ) and a negative edge synchronized by the second clock signal (CLK 2 ). The positive single-edge latch ( 200 ) and the negative single-edge latch ( 300 ) are also presented.
1 . A differential driver circuit configured for use in a digital to analog conversion (DAC) cell, wherein:
the differential driver circuit comprises a first single-ended driver circuit and a second single-ended driver circuit;
the first single-ended driver circuit is configured to receive a data signal;
the second single-ended driver circuit is configured to receive an inverse of the data signal; and
each of the first and second single-ended driver circuits comprises the following:
a positive single-edge latch configured to receive the data signal or the inverse and to provide a positive edge latched data signal based on the received data signal or inverse, said latch comprising a high side drive transistor controlled by an output signal provided between a first high side transistor switch and a series connection of a first low side transistor switch and a second low side transistor switch, wherein:
the first high side transistor switch and the second low side transistor switch are configured to be controlled by the data signal or the inverse, and the first low side transistor switch is configured to be controlled by a first clock signal;
the first high side transistor switch is configured to be activated by a low state of the data signal or the inverse;
the second low side transistor switch is configured to be activated by a high state of the data signal or the inverse; and
the first low side transistor switch is configured to be activated by a high state of the first clock signal,
wherein the high side drive transistor is arranged to provide the positive edge latched data signal at an open drain terminal of the high side drive transistor; and
a negative single-edge latch configured to receive the data signal or the inverse and to provide a negative edge latched data signal based on the received data signal or inverse, said latch comprising a low side drive transistor controlled by a negative output signal provided between a further first low side transistor switch and a series connection of a further first high side transistor switch and a further second high side transistor switch, wherein:
the further first high side transistor switch and the further first low side transistor switch are configured to be controlled by the data signal or the inverse, and the further second high side transistor switch is configured to be controlled by a second clock signal;
the further first high side transistor switch is configured to be activated by a low state of the data signal or the inverse;
the further first low side transistor switch is configured to be activated by a high state of the data signal or the inverse; and
the further second high side transistor switch is configured to be activated by a low state of the second clock signal,
wherein the low side drive transistor is arranged to provide the negative edge latched data signal at an open drain terminal of the low side drive transistor;
wherein the drain terminals of said high side drive transistor and said low side drive transistor are interconnected.
2 . The differential driver circuit of claim 1 , wherein for each of the first and second single-ended driver circuits, in the positive single-edge latch, the first low side transistor switch is arranged upstream of the second low side transistor switch.
3 . The differential driver circuit of claim 1 , wherein for each of the first and second single-ended driver circuits, the positive single-edge latch further comprises a second high side transistor switch operatively connected in parallel with the first high side transistor and the first low side transistor switch, wherein the second high side transistor switch is configured to be controlled by the data signal or the inverse.
4 . The differential driver circuit of claim 1 , wherein for each of the first and second single-ended driver circuits, in the negative single-edge latch, the first high side transistor switch is arranged upstream of the second high side transistor switch.
5 . The differential driver circuit of claim 1 , wherein for each of the first and second single-ended driver circuits, the negative single-edge latch further comprises a second low side transistor switch operatively connected in parallel with the second high side transistor and the first low side transistor switch, wherein the second low side transistor switch is configured to be controlled by the data signal or the inverse.
6 . The differential driver circuit of claim 1 , wherein for each of the first and second single-ended driver circuits, the second clock signal is inverted in relation to the first clock signal.
7 . The differential driver circuit of claim 1 , wherein for each of the first and second single-ended driver circuits, the second clock signal is delayed by a delay period in relation to the first clock signal.
8 . The differential driver circuit of claim 7 , wherein for each of the first and second single-ended driver circuits, the delay period is configurable.
9 . The differential driver circuit of claim 1 , wherein for each of the first and second single-ended driver circuits, in the positive single-edge latch, the first low side transistor switch is arranged upstream of the second low side transistor switch.
10 . The differential driver circuit of claim 1 , wherein:
for each of the first and second single-ended driver circuits, the positive single-edge latch further comprises a second high side transistor switch operatively connected in parallel with the first high side transistor and the first low side transistor switch;
for the first single-ended driver circuit, the second high side transistor switch is configured to be controlled by the data signal; and
for the second single-ended driver circuit, the second high side transistor switch is configured to be controlled by the inverse D.
11 . The differential driver circuit of claim 1 , wherein for each of the first and second single-ended driver circuits, in the negative single-edge latch, the first high side transistor switch is arranged upstream of the second high side transistor switch.
12 . The differential driver circuit of claim 1 , wherein:
for each of the first and second single-ended driver circuits, the negative single-edge latch further comprises a second low side transistor switch operatively connected in parallel with the second high side transistor and the first low side transistor switch;
for the first single-ended driver circuit, the second low side transistor switch is configured to be controlled by the data signal; and
for the second single-ended driver circuit, the second low side transistor switch is configured to be controlled by the inverse D.
13 . A digital to analog converter comprising one or more digital-to-analog conversion (DAC) cells and the differential driver circuit of claim 1 , wherein at least one of the DAC-cells is controlled by the differential driver circuit.
14 . The digital to analog converter of claim 13 , further comprising a clock distribution circuit configured to receive a main clock signal and to provide the first clock signal and the second clock signal based on the main clock signal.
15 . An integrated circuit comprising the digital to analog converter of claim 13 .
16 . A network node comprising the digital to analog converter of claim 13 .
17 . A wireless device comprising the digital to analog converter of claim 13 .