Methods and apparatuses for operating analog-to-digital converters in an ultrasound device with timing delays
Aspects of the technology described herein relate to an ultrasound device having a first analog-to-digital converter (ADC) configured to operate with a first ADC clock signal having a first timing delay and a second ADC configured to operate with a second ADC clock signal having a second timing delay. The first timing delay and the second timing delay may be different. The ultrasound device may further include delay control circuitry configured to control direct digital synthesis (DDS) circuitry to implement a first delay in ultrasound data from the first ADC and a second delay in ultrasound data from the second ADC. The first delay may correct for the first timing delay and the second delay may correct for the second timing delay.
1 . An ultrasound device, comprising:
a plurality of ultrasonic transducers incorporated together on an integrated circuit chip or one or more integrated circuit chips packaged together, the plurality of ultrasonic transducers being configured to obtain analog ultrasound echo signals for use in generating ultrasound images;
a first plurality of analog-to-digital converters (ADC) coupled to a first set of the plurality of ultrasonic transducers and configured to operate with a same first ADC clock signal having a first timing delay;
a second plurality of ADCs coupled to a second set of the plurality of ultrasonic transducers and configured to operate with a same second ADC clock signal having a second timing delay different than the first timing delay; and
digital processing circuitry configured to process digital ultrasound data from the first and second pluralities of ADCs;
wherein the first timing delay and the second timing delay differ by a fraction of a sampling clock period such that sample-and-hold operations of the first plurality of ADCs and the second plurality of ADCs begin at different times within the sampling clock period to reduce sampling-related noise; and wherein the digital processing circuitry is configured to compensate for the different times of the sample-and-hold operations by applying a digital delay to the digital ultrasound data that is substantially equal to an amount of time represented by the first or second timing delay but in an opposite time direction.
2 . The ultrasound device of claim 1 , wherein the first plurality of ADCs is configured to operate with the first ADC clock signal and the second plurality of ADCs is configured to operate with the second ADC clock signal, such that sample and hold operations of the first plurality of ADCs and the second plurality of ADCs start at times that are different by a fraction of a sampling clock period.
3 . The ultrasound device of claim 1 , wherein the first plurality of ADCs is in one ultrasound processing unit (UPU) and the second plurality of ADCs is in another UPU.
4 . The ultrasound device of claim 1 , wherein the first plurality of ADCs and the second plurality of ADCs are in a single ultrasound processing unit (UPU).
5 . The ultrasound device of claim 1 , further comprising:
first clocking circuitry configured to provide the first ADC clock signal to the first plurality of ADCs; and
second clocking circuitry configured to provide the second ADC clock signal to the second plurality of ADCs.
6 . The ultrasound device of claim 1 , further comprising:
clocking circuitry configured to provide the first ADC clock signal to the first plurality of ADCs and the second ADC clock signal to the second plurality of ADCs.
7 . The ultrasound device of claim 1 , wherein the first ADC clock signal and the second ADC clock signal are derived from a system clock.
8 . The ultrasound device of claim 1 , wherein the first ADC clock signal and the second ADC clock signal are generated by a phase-locked loop (PLL).
9 . The ultrasound device of claim 1 , wherein the first ADC clock signal and the second ADC clock signal have a same frequency.
10 . The ultrasound device of claim 1 , further comprising:
first direct digital synthesis (DDS) circuitry;
first delay control circuitry configured to control the first DDS circuitry to implement a first delay in the digital ultrasound data from the first plurality of ADCs;
second DDS circuitry; and
second delay control circuitry configured to control the second DDS circuitry to implement a second delay in the digital ultrasound data from the second plurality of ADCs;
wherein the first delay and the second delay are different.
11 . The ultrasound device of claim 1 , further comprising:
direct digital synthesis (DDS) circuitry; and
delay control circuitry configured to control the DDS circuitry to implement a first delay in the digital ultrasound data from the first plurality of ADCs and a second delay in the digital ultrasound data from the second plurality of ADCs.
12 . The ultrasound device of claim 11 , wherein:
the first delay corrects for the first timing delay; and
the second delay corrects for the second timing delay.
13 . The ultrasound device of claim 11 , wherein:
an amount of the first delay is substantially equal to an amount of time represented by the first timing delay and in an opposite time direction; and
an amount of the second delay is substantially equal to an amount of time represented by the second timing delay and in an opposite time direction.
14 . The ultrasound device of claim 11 , wherein:
the first delay includes a delay for correcting for the first timing delay and a delay for beamforming the digital ultrasound data from the first plurality of ADCs; and
the second delay includes a delay for correcting for the second timing delay and a delay for beamforming the digital ultrasound data from the second plurality of ADCs.
15 . The ultrasound device of claim 11 , wherein:
the first timing delay represents a delay forward in time and the first delay is backward in time; or
the first timing delay represents a delay backward in time and the first delay is forward in time.
16 . The ultrasound device of claim 1 , further comprising:
beamforming circuitry configured to implement a first delay in the digital ultrasound data from the first plurality of ADCs and a second delay in the digital ultrasound data from the second plurality of ADCs;
wherein the first delay and the second delay are different.
17 . The ultrasound device of claim 16 , wherein:
the first delay includes a delay for correcting for the first timing delay and a delay for beamforming the digital ultrasound data from the first plurality of ADCs; and
the second delay includes a delay for correcting for the second timing delay and a delay for beamforming the digital ultrasound data from the second plurality of ADCs.
18 . The ultrasound device of claim 17 , wherein interpolation filters, linear interpolation, or fractional delay filters are used to correct for the first timing delay and the second timing delay.
19 . The ultrasound device of claim 1 , wherein the first plurality of ADCs and the second plurality of ADCs are configured to operate simultaneously using the first ADC clock signal and the second ADC clock signal, respectively.
20 . The ultrasound device of claim 1 , wherein the first ADC clock signal and the second ADC clock signal are strobe signals.
21 . The ultrasound device of claim 1 , wherein the ultrasound device comprises an ultrasound-on-chip.
22 . The ultrasound device of claim 21 , wherein the ultrasound-on-chip comprises the first plurality of ADCs and the second plurality of ADCs and a plurality of ultrasonic transducers.
23 . The ultrasound device of claim 1 , wherein the ultrasound device comprises an ultrasound-on-chip including hundreds of ADCs, thousands of ADCs, or tens of thousands of ADCs.