Sample and hold circuit and related driver circuit
A sample and hold (S/H) circuit includes an analog-to-digital converter (ADC), a register and a digital-to-analog converter (DAC). The ADC receives an input signal and converts the input signal into a digital code. The register, coupled to the ADC, stores the digital code. The DAC, coupled to the register, converts the digital code into an output signal.
1 . A sample and hold (S/H) circuit, comprising:
an analog-to-digital converter (ADC), to receive an input signal and convert the input signal into a digital code;
a register, coupled to the ADC, to store the digital code;
a digital-to-analog converter (DAC), coupled to the register, to convert the digital code into an output signal; and
a current-to-voltage converter, coupled between the ADC and an input terminal of the S/H circuit, to convert an input current of the S/H circuit into a voltage to serve as the input signal;
wherein the current-to-voltage converter comprises a transistor, of which a gate terminal and a drain terminal are coupled to each other and further coupled to an input terminal of the ADC.
2 . The S/H circuit of claim 1 , wherein the ADC converts the input signal into the digital code in a sampling period, and the DAC converts the digital code into the output signal in a holding period following the sampling period.
3 . The S/H circuit of claim 1 , wherein the register comprises a latch circuit.
4 . The S/H circuit of claim 1 , wherein the output signal is an output current.
5 . The S/H circuit of claim 1 , further comprising:
a sampling switch, coupled to the ADC, to be turned on in a sampling period; and
an output enable switch, coupled to the DAC, to be turned on in a holding period following the sampling period.
6 . The S/H circuit of claim 1 , wherein the DAC comprises:
a plurality of control switches, each controlled according to the digital code; and
a plurality of current sources, each coupled to one of the plurality of control switches.
7 . The S/H circuit of claim 1 , wherein the DAC comprises:
a plurality of control switches, each coupled to a first node or a second node according to the digital code;
a plurality of resistors, each coupled to one of the plurality of control switches, to generate an output voltage; and
an operational amplifier, coupled to the plurality of resistors, to generate an output current according to the output voltage.
8 . The S/H circuit of claim 1 , wherein the S/H circuit outputs the output signal as an output current to one of a plurality of channels of a light-emitting diode (LED) panel.