Error decoding with iterative parameter updating
An error-handling module of a controller determines that a codeword received from a memory device has errors. The error-handing module assigs an initial set of log-likelihood ratios (LLRs) to bits of the codeword based on a column weight (CW) of a low density parity check (LDPC) code. The error-handling module updates the LLRs based on parity check outcomes. The controller decodes embedded data from the codeword based on the updated LLRs.
1 . A method for decoding data, comprising:
determining by an error-handling module of a controller, that a codeword received from a memory device has errors;
assigning, by the error-handling module responsive to the determining, an initial set of log-likelihood ratios (LLRs) representing logarithmic ratios of likelihoods that indicate a probability of each bit having a particular binary value to individual bits of the codeword based on a column weight (CW) of each respective bit of a low density parity check (LDPC) code, wherein a first portion of bits of the codeword have a CW that is below a threshold, and the first portion of bit are assigned LLR values from a first LLR set having multiple values over a first magnitude range and a second portion of bits of the codeword have a CW that meets or exceeds the threshold, the second portion of the bits are assigned LLR values from a second LLR set having multiple values over a second magnitude range that is smaller than the first magnitude range;
responsive to the assigning, iteratively updating, by the error-handling module, the LLRs based on parity check outcomes; and
decoding, by the controller, embedded data from the codeword based on the updated LLRs.
2 . The method of claim 1 , further comprising reading, by the controller, the codeword from a memory device.
3 . The method of claim 1 , wherein the LLRs of the first set of LLRs and the second set of LLRs are integers, wherein bits associated with the second set of LLRs are flipped in fewer iterations of the iteratively updating than bits associated with the first set of LLRs.
4 . The method of claim 1 , wherein the assigning is executed in response to a failed decoding for the codeword in which each bit of the codeword is assigned a same LLR set, and the LLRs are updated using a MinSum decoding process.
5 . The method of claim 1 , wherein bits of the codeword are assigned a given set of LLRs of at least three sets of LLRs based on the CW of a corresponding bit.
6 . The method of claim 1 , wherein values of the LLRs of the first LLR set and the second LLR set are based on error rates of bits of the memory device that have LLR values with magnitudes corresponding to a greatest magnitude values within a respective one of the first LLR set or the second LLR set.
7 . The method of claim 1 , further comprising:
detecting, by the controller, that the errors of the codeword have been corrected by the decoding; and
returning, by the controller, embedded data of the codeword responsive to the detecting.
8 . A system for decoding data stored in a memory device, comprising:
a memory device; and
a processing device coupled to the memory, the processing device to perform operations comprising:
determining by an error-handling module of a controller, that a codeword received from a memory device has errors;
assigning, responsive to the determining, an initial set of log-likelihood ratios (LLRs) representing logarithmic ratios of likelihoods that indicate a probability of each bit having a particular binary value to individual bits of the codeword based on a column weight (CW) each respective bit of a low density parity check (LDPC) code, wherein a first portion of bits of the codeword have a CW that is below a threshold, and the first portion of bit are assigned LLR values from a first LLR set having multiple values over a first magnitude range and a second portion of bits of the codeword have a CW that meets or exceeds the threshold, the second portion of the bits are assigned LLR values from a second LLR set having multiple values over a second magnitude range that is smaller than the first magnitude range;
responsive to the assigning, iteratively updating the LLRs based on parity check outcomes; and
decoding embedded data from the codeword based on the updated LLRs.
9 . The system of claim 8 , the operations further comprising reading the codeword from a memory device.
10 . The system of claim 8 , wherein the LLRs of the first set of LLRs and the second set of LLRs are integers, and the bits associated with the second set of LLRs are flipped in fewer iterations of the iteratively updating than bits associated with the first set of LLRs.
11 . The system of claim 8 , wherein the assigning is executed in response to a failed decoding for the codeword in which each bit of the codeword is assigned a same LLR set.
12 . The system of claim 8 , wherein values of the LLRs of the first LLR set and the second LLR set are based on error rates of bits of the memory device that have LLR values with magnitudes corresponding to a greatest magnitude values within a respective one of the first LLR set or the second LLR set.
13 . The system of claim 8 , the operations further comprising:
detecting that the errors of the codeword have been corrected by the decoding; and
returning embedded data of the codeword responsive to the detecting.
14 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
determining by an error-handling module of a controller, that a codeword received from a memory device has errors;
assigning, by the error-handling module responsive to the determining, an initial set of log-likelihood ratios (LLRs) representing logarithmic ratios of likelihoods that indicate a probability of each bit having a particular binary value to individual bits of the codeword based on a column weight (CW) of each respective bit of a low density parity check (LDPC) code, wherein a first portion of bits of the codeword have a CW that is below a threshold, and the first portion of bit are assigned LLR values from a first LLR set having multiple values over a first magnitude range and a second portion of bits of the codeword have a CW that meets or exceeds the threshold, the second portion of the bits are assigned LLR values from a second LLR set having multiple values over a second magnitude range that is smaller than the first magnitude range;
responsive to the assigning, iteratively updating, by the error-handling module, the LLRs based on parity check outcomes; and
decoding, by the controller, data from the codeword based on the updated LLRs.
15 . The non-transitory computer-readable storage medium of claim 14 , wherein the processing device is to perform operations further comprising:
reading the codeword from a memory device.
16 . The non-transitory computer-readable storage medium of claim 14 , wherein the LLRs of the first set of LLRs and the second set of LLRs are integers.
17 . The non-transitory computer-readable storage medium of claim 14 , wherein values of the LLRs of the first LLR set and the second LLR set are based on error rates of the memory device that have LLR values with magnitudes corresponding to a greatest magnitude values within a respective one of the first LLR set or the second LLR set.