Falling-edge modulation signal receiver and falling-edge modulation signal sampling method
A falling-edge modulation signal receiver is configured to process an input signal having a duty cycle varying with a bit value of the input signal. The receiver includes: a phase-locked loop for generating an oversampling clock according to the input signal which correlates with a signal clock, wherein the oversampling frequency is not lower than five times the frequency of the signal clock; an oversampling circuit for sampling the input signal according to the oversampling clock and thereby generating multiple groups of data which as a whole is corresponding to a single bit of the input signal; and a decision circuit for ascertaining that X bits of the multiple groups of data are 1 and determining the value of the single bit according to the X. When the X is greater/less than a threshold, the decision circuit determines that the value of the single bit is 1/0.
1 . A falling-edge modulation signal receiver configured to process an input signal having a current duty cycle which varies with a current bit value of the input signal based on falling-edge modulation, the falling-edge modulation signal receiver including:
a phase-locked loop configured to generate an oversampling clock according to the input signal, wherein the input signal correlates with a signal clock, an oversampling frequency is equal to N times a frequency of the signal clock, and the N is a positive number equal to or greater than five;
an oversampling circuit configured to receive the oversampling clock and the input signal and then sample the input signal according to the oversampling clock so as to generate M group(s) of data in one cycle of the input signal, wherein the M group(s) of data as a whole is corresponding to one single bit of the input signal, each group of the M group(s) of data includes K sample bit(s), a value of each of the K sample bit(s) is a first bit value or alternatively a second bit value, both the M and the K are positive integers, and a product the M and the K is equal to an integral component of the N; and
a decision circuit configured to analyze the M group(s) of data and thereby ascertain there is/are X sample bit(s) of the M group(s) of data having the first bit value and determine a value of the one single bit of the input signal according to the X, wherein the X is a positive integer, when the decision circuit finds that the X satisfies a condition, the decision circuit determines that the value of the one single bit of the input signal is the first bit value, and when the decision circuit finds that the X does not satisfy the condition, the decision circuit determines that the value of the one single bit of the input signal is the second bit value,
wherein the N is equal to or greater than forty, the M is equal to or greater than four, and the K is equal to or greater than ten.
2 . The falling-edge modulation signal receiver of claim 1 , wherein the input signal originates from an HDMI enhanced Audio Return Channel (eARC) differential signal.
3 . The falling-edge modulation signal receiver of claim 1 , wherein the first bit value is one and the second bit value is zero; when the X is greater than a predetermined value, the decision circuit determines that the X satisfies the condition; and when the X is not greater than the predetermined value, the decision circuit determines that the X does not satisfy the condition.
4 . The falling-edge modulation signal receiver of claim 1 , wherein the first bit value is zero and the second bit value is one; when the X is greater than a predetermined value, the decision circuit determines that the X satisfies the condition; and when the X is not greater than the predetermined value, the decision circuit determines that the X does not satisfy the condition.
5 . A falling-edge modulation signal receiver configured to process an input signal having a current duty cycle which varies with a current bit value of the input signal based on falling-edge modulation, the falling-edge modulation signal receiver including:
a phase-locked loop configured to generate an oversampling clock according to the input signal, wherein the input signal correlates with a signal clock, an oversampling frequency is equal to N times a frequency of the signal clock, and the N is a positive number equal to or greater than five;
an oversampling circuit configured to receive the oversampling clock and the input signal and then sample the input signal according to the oversampling clock so as to generate M group(s) of data in one cycle of the input signal, wherein the M group(s) of data as a whole is corresponding to one single bit of the input signal, each group of the M group(s) of data includes K sample bit(s), a value of each of the K sample bit(s) is a first bit value or alternatively a second bit value, both the M and the K are positive integers, and a product the M and the K is equal to an integral component of the N; and
a decision circuit configured to analyze the M group(s) of data and thereby ascertain there is/are X sample bit(s) of the M group(s) of data having the first bit value and determine a value of the one single bit of the input signal according to the X, wherein the X is a positive integer, when the decision circuit finds that the X satisfies a condition, the decision circuit determines that the value of the one single bit of the input signal is the first bit value, and when the decision circuit finds that the X does not satisfy the condition, the decision circuit determines that the value of the one single bit of the input signal is the second bit value,
wherein the decision circuit includes a tree adder configured to derive the X from the M group(s) of data.
6 . A falling-edge modulation signal receiver configured to process an input signal having a current duty cycle which varies with a current bit value of the input signal based on falling-edge modulation, the falling-edge modulation signal receiver including:
a phase-locked loop configured to generate an oversampling clock according to the input signal, wherein the input signal correlates with a signal clock, an oversampling frequency is equal to N times a frequency of the signal clock, and the N is a positive number equal to or greater than five;
an oversampling circuit configured to receive the oversampling clock and the input signal and then sample the input signal according to the oversampling clock so as to generate M group(s) of data in one cycle of the input signal, wherein the M group(s) of data as a whole is corresponding to one single bit of the input signal, each group of the M group(s) of data includes K sample bit(s), a value of each of the K sample bit(s) is a first bit value or alternatively a second bit value, both the M and the K are positive integers, and a product the M and the K is equal to an integral component of the N; and
a decision circuit configured to analyze the M group(s) of data and thereby ascertain there is/are X sample bit(s) of the M group(s) of data having the first bit value and determine a value of the one single bit of the input signal according to the X, wherein the X is a positive integer, when the decision circuit finds that the X satisfies a condition, the decision circuit determines that the value of the one single bit of the input signal is the first bit value, and when the decision circuit finds that the X does not satisfy the condition, the decision circuit determines that the value of the one single bit of the input signal is the second bit value,
wherein the decision circuit includes:
a bubble removing circuit configured to determine whether any group of the M group(s) of data is erroneous,
wherein when a certain group of the M group(s) of data is found erroneous, the bubble removing circuit replaces the certain group of the M group(s) of data with a group of bubble-cleaned data.
7 . The falling-edge modulation signal receiver of claim 6 , wherein the bubble removing circuit compares each group of multiple groups of predetermined data with the certain group of the M group(s) of data and thereby generates multiple differentials; and the bubble removing circuit searches prestored data according to a minimum differential of the multiple differentials to obtain the group of bubble-cleaned data corresponding to the minimum differential.
8 . The falling-edge modulation signal receiver of claim 7 , wherein the bubble removing circuit includes:
a buffer circuit configured to temporarily store the certain group of the M group(s) of data;
a storage circuit configured to store the multiple groups of predetermined data;
a likelihood decoding circuit configured to compare the each group of the multiple groups of predetermined data with the certain group of the M group(s) of data and thereby generates the multiple differentials; and
a minimum solving circuit configured to determine the minimum differential of the multiple differentials and thereby output the group of bubble-cleaned data.
9 . The falling-edge modulation signal receiver of claim 6 , wherein the decision circuit further includes a voting circuit configured to obtain the X according to variations in bit values of the M group(s) of data and then determine whether the X satisfies the condition.
10 . The falling-edge modulation signal receiver of claim 9 , wherein the voting circuit includes:
a look-up-table and edge-detection circuit configured to generate at least one count value and an edge-detection signal according to the group of bubble-cleaned data;
a control circuit configured to generate a control signal according to the edge-detection signal; and
a counting circuit configured to operate in a boundary mode or alternatively a non-boundary mode according to the control signal, and thereby generate the value of the one single bit of the input signal according to the at least one count value.