Method and system for setting digital equalizer

1 . A method for setting a digital equalizer, the method being applicable to a signal receiver, the signal receiver including a digital signal processor, the digital signal processor including a target digital equalizer, the target digital equalizer having an equalizer coefficient, and the method comprising:

configuring, during a simulation phase, a first electronic device as a link partner to sequentially select one of a plurality of preset transmission channels for connection with the signal receiver, and configuring a second electronic device to execute a search program each time when the first electronic device is connected to the signal receiver via one of the plurality of preset transmission channels, so as to obtain a plurality of coefficient initial values and a plurality of coefficient limit values that respectively correspond to the plurality of preset transmission channels; and

configuring, during a connection phase, a processor to set the equalizer coefficient of the target digital equalizer according to one of the plurality of coefficient initial values and one of the plurality of coefficient limit values corresponding to one of the plurality of preset transmission channels.

2 . The method according to claim 1 , wherein the connection phase is a phase in which the signal receiver receives signals from a signal transmitter via a current transmission channel; wherein the process of the processor setting the equalizer coefficient of the target digital equalizer according to one of the plurality of coefficient initial values and one of the plurality of coefficient limit values corresponding to one of the plurality of preset transmission channels includes:

determining whether or not one of the plurality of preset transmission channels matches the current transmission channel, and setting, in response to determining that one of the plurality of preset transmission channels matches the current transmission channel, the equalizer coefficient of the target digital equalizer according to one of the plurality of coefficient initial values and one of the plurality of coefficient limit values corresponding to one of the plurality of preset transmission channels that matches the current transmission channel.

3 . The method according to claim 2 , wherein the signal receiver further includes:

an analog-to-digital convertor coupled to the digital signal processor, wherein the analog-to-digital convertor is configured to convert an analog reception signal into a digital input signal according to a sampling phase; wherein the target digital equalizer receives the digital input signal, and outputs a slicer input signal after filtering of inter-symbol interference; and

a clock recovery circuit coupled to the digital signal processor and the analog-to-digital converter, wherein the clock recovery circuit is configured to provide the sampling phase.

4 . The method according to claim 3 , wherein the search program executed by the second electronic device each time when the first electronic device is connected to the signal receiver via one of the plurality of preset transmission channels includes processes of:

switching the clock recovery circuit with the second electronic device for providing the sampling phase to the analog-to-digital converter, and sequentially selecting, by the second electronic device, one of a plurality of preset phases as the sampling phase to be provided to the analog-to-digital converter;

configuring the first electronic device to transmit an analog transmission signal;

determining whether or not the signal receiver receives the analog reception signal;

using, in response to determining that the signal receiver receives the analog reception signal, one of the plurality of preset phases that is currently provided to the analog-to-digital converter as a phase zero;

resetting the equalizer coefficient of the target digital equalizer;

configuring the target digital equalizer to perform an automatic update of the equalizer coefficient;

determining whether or not the equalizer coefficient of the target digital equalizer achieves coefficient convergence; and

recording, in response to determining that the equalizer coefficient of the target digital equalizer achieves the coefficient convergence, a signal-to-noise ratio and a coefficient convergence value of the target digital equalizer in one of the plurality of preset phases that is currently provided to the analog-to-digital converter.

5 . The method according to claim 4 , wherein the search program executed by the second electronic device each time when the first electronic device is connected to the signal receiver via one of the plurality of preset transmission channels further includes processes of:

determining whether or not each of the plurality of preset phases is already provided to the analog-to-digital converter as the sampling phase;

stopping, in response to determining that not each of the plurality of preset phases is already provided to the analog-to-digital converter as the sampling phase, the target digital equalizer from performing the automatic update of the equalizer coefficient, and changing one of the plurality of preset phases that is currently provided to the analog-to-digital converter; and

re-executing, after changing one of the plurality of preset phases that is currently provided to the analog-to-digital converter, the process of resetting the equalizer coefficient of the target digital equalizer.

6 . The method according to claim 5 , wherein the search program executed by the second electronic device each time when the first electronic device is connected to the signal receiver via one of the plurality of preset transmission channels further includes processes of:

selecting, in response to determining that each of the plurality of preset phases is already provided to the analog-to-digital converter as the sampling phase, the coefficient convergence value in one of the plurality of preset phases that has a maximum one of signal-to-noise ratios as one of the plurality of coefficient initial values corresponding to one of the plurality of preset transmission channels, and selecting, within a range in which one of the plurality of preset phases that has the maximum one of the signal-to-noise ratios acts as a center, a maximum one of the coefficient convergence value and a minimum one of the coefficient convergence value as an upper limit value and a lower limit value of the coefficient limit value corresponding to one of the plurality of preset transmission channels; and

writing one of the plurality of coefficient initial values and one of the plurality of coefficient limit values corresponding to one of the plurality of preset transmission channels into a memory of the signal receiver.

7 . A system for setting a digital equalizer, the system being applicable to a signal receiver, the signal receiver including a digital signal processor, the digital signal processor including a target digital equalizer, the target digital equalizer having an equalizer coefficient, and the system comprising:

a first electronic device, wherein, during a simulation phase, the first electronic device is configured as a link partner to sequentially select one of a plurality of preset transmission channels for connection with the signal receiver;

a second electronic device coupled to the first electronic device and the signal receiver during the simulation phase, wherein the second electronic device is configured to execute a search program each time when the first electronic device is connected to the signal receiver via one of the plurality of preset transmission channels, so as to obtain a plurality of coefficient initial values and a plurality of coefficient limit values that respectively correspond to one of the plurality of preset transmission channels; and

a processor disposed in the signal receiver, wherein, during a connection phase, the processor is configured to set the equalizer coefficient of the target digital equalizer according to one of the plurality of coefficient initial values and one of the plurality of coefficient limit value corresponding to one of the plurality of preset transmission channels.

8 . The system according to claim 7 , wherein the connection phase is a phase in which the signal receiver receives signals from a signal transmitter via a current transmission channel; wherein the process of the processor setting the equalizer coefficient of the target digital equalizer according to one of the plurality of coefficient initial values and one of the plurality of coefficient limit values corresponding to one of the plurality of preset transmission channels includes:

determining whether or not one of the plurality of preset transmission channels matches the current transmission channel, and setting, in response to determining that one of the plurality of preset transmission channels matches the current transmission channel, the equalizer coefficient of the target digital equalizer according to one of the plurality of coefficient initial values and one of the plurality of coefficient limit values corresponding to one of the plurality of preset transmission channels that matches the current transmission channel.

9 . The system according to claim 8 , wherein the signal receiver further includes:

an analog-to-digital convertor coupled to the digital signal processor, wherein the analog-to-digital convertor is configured to convert an analog reception signal into a digital input signal according to a sampling phase; wherein the target digital equalizer receives the digital input signal, and outputs a slicer input signal after filtering of inter-symbol interference; and

a clock recovery circuit coupled to the digital signal processor and the analog-to-digital converter, wherein the clock recovery circuit is configured to provide the sampling phase.

10 . The system according to claim 9 , wherein the search program executed by the second electronic device each time when the first electronic device is connected to the signal receiver via one of the plurality of preset transmission channels includes processes of:

switching the clock recovery circuit with the second electronic device for providing the sampling phase to the analog-to-digital converter, and sequentially selecting, by the second electronic device, one of a plurality of preset phases as the sampling phase to be provided to the analog-to-digital converter;

configuring the first electronic device to transmit an analog transmission signal;

determining whether or not the signal receiver receives the analog reception signal;

using, in response to determining that the signal receiver receives the analog reception signal, one of the plurality of preset phases that is currently provided to the analog-to-digital converter as a phase zero;

resetting the equalizer coefficient of the target digital equalizer;

configuring the target digital equalizer to perform an automatic update of the equalizer coefficient;

determining whether or not the equalizer coefficient of the target digital equalizer achieves coefficient convergence; and

recording, in response to determining that the equalizer coefficient of the target digital equalizer achieves the coefficient convergence, a signal-to-noise ratio and a coefficient convergence value of the target digital equalizer in one of the plurality of preset phases that is currently provided to the analog-to-digital converter.

11 . The system according to claim 10 , wherein the search program executed by the second electronic device each time when the first electronic device is connected to the signal receiver via one of the plurality of preset transmission channels further includes processes of:

determining whether or not each of the plurality of preset phases is already provided to the analog-to-digital converter as the sampling phase;

stopping, in response to determining that not each of the plurality of preset phases is already provided to the analog-to-digital converter as the sampling phase, the target digital equalizer from performing the automatic update of the equalizer coefficient, and changing one of the plurality of preset phases that is currently provided to the analog-to-digital converter; and

re-executing, after changing one of the plurality of preset phases that is currently provided to the analog-to-digital converter, the process of resetting the equalizer coefficient of the target digital equalizer.

12 . The system according to claim 11 , wherein the search program executed by the second electronic device each time when the first electronic device is connected to the signal receiver via one of the plurality of preset transmission channels further includes processes of:

selecting, in response to determining that each of the plurality of preset phases is already provided to the analog-to-digital converter as the sampling phase, the coefficient convergence value in one of the plurality of preset phases that has a maximum one of signal-to-noise ratios as one of the plurality of coefficient initial values corresponding to one of the plurality of preset transmission channels, and selecting, within a range in which one of the plurality of preset phases that has the maximum one of the signal-to-noise ratios acts as a center, a maximum one of the coefficient convergence value and a minimum one of coefficient convergence value as an upper limit value and a lower limit value of the coefficient limit value corresponding to one of the plurality of preset transmission channels; and

writing one of the plurality of coefficient initial values and one of the plurality of coefficient limit values corresponding to one of the plurality of preset transmission channels into a memory of the signal receiver.

13 . The system according to claim 7 , further comprising:

an oscillator, wherein the oscillator is configured to provide a clock rate to the first electronic device and the signal receiver during the simulation phase.