Floating tap partially rolled digital feedback equalization architecture
The present disclosure relates to a floating tap, partially rolled digital feedback equalization circuit and method of using the same. The circuit may include an analog front end circuit and a digital circuit in electrical communication with the analog front end circuit, wherein the analog front end circuit includes a first unrolled tap and a plurality of rolled taps.
1 . A floating tap partially rolled digital feedback equalization circuit comprising:
an analog front end circuit;
a digital circuit in electrical communication with the analog front end circuit, wherein the analog front end circuit includes a first unrolled tap and a plurality of rolled taps; and
an interleaved structure configured to allow data sampling using a rising and a falling edge of a sampling clock, wherein the interleaved structure received data from two separate receivers associated with one or more equalizer taps that are associated with one or more of the first unrolled tap and the plurality of rolled taps.
2 . The floating tap partially rolled digital feedback equalization circuit of claim 1 , wherein the analog front end circuit includes a plurality of fixed taps.
3 . The floating tap partially rolled digital feedback equalization circuit of claim 1 , wherein the analog front end circuit includes a plurality of floating taps.
4 . The floating tap partially rolled digital feedback equalization circuit of claim 1 , wherein the plurality of rolled taps includes 3 rolled taps.
5 . The floating tap partially rolled digital feedback equalization circuit of claim 1 , wherein data is sampled using the rising edge is EVEN data.
6 . The floating tap partially rolled digital feedback equalization circuit of claim 1 , wherein data is sampled using the falling edge is ODD data.
7 . The floating tap partially rolled digital feedback equalization circuit of claim 1 , wherein the analog front end circuit includes four comparators.
8 . The floating tap partially rolled digital feedback equalization circuit of claim 1 , wherein one or more preamble bits are used to generate a digital feedback equalization offset for one or more initial data bits.
9 . The floating tap partially rolled digital feedback equalization circuit of claim 1 , wherein one or more postamble bits are used to generate a digital feedback equalization offset for one or more initial data bits.
10 . A floating tap partially rolled digital feedback equalization method comprising:
providing an analog front end circuit;
electrically connecting the analog front end circuit with a digital circuit, wherein the analog front end circuit includes a plurality of unrolled taps and a plurality of rolled taps; and
data sampling, via an interleaved structure, using a rising and a falling edge of a sampling clock, wherein the interleaved structure received data from two separate receivers associated with one or more equalizer taps that are associated with one or more of the plurality of unrolled taps and the plurality of rolled taps.
11 . The floating tap partially rolled digital feedback equalization method of claim 10 , wherein the analog front end circuit includes a plurality of fixed taps.
12 . The floating tap partially rolled digital feedback equalization method of claim 10 , wherein the analog front end circuit includes a plurality of floating taps.
13 . The floating tap partially rolled digital feedback equalization method of claim 10 , wherein the plurality of rolled taps includes 3 rolled taps.
14 . The floating tap partially rolled digital feedback equalization method of claim 10 , wherein data is sampled using the rising edge is EVEN data.
15 . The floating tap partially rolled digital feedback equalization method of claim 10 , wherein data is sampled using the falling edge is ODD data.
16 . The floating tap partially rolled digital feedback equalization method of claim 10 , wherein the analog front end circuit includes four comparators.
17 . The floating tap partially rolled digital feedback equalization method of claim 10 , wherein one or more preamble bits are used to generate a digital feedback equalization offset for one or more initial data bits.
18 . The floating tap partially rolled digital feedback equalization method of claim 10 , wherein one or more postamble bits are used to generate a digital feedback equalization offset for one or more initial data bits.