Image sensor
Disclosed is an image sensor including a buffer circuit suitable for generating, based on at least one first signal, at least one second signal controlled during each of settling and comparison periods, a comparison circuit suitable for using an operating current having a relatively high level during the settling period and a relatively low level during the comparison period based on the second signal, and comparing a pixel signal with a ramp signal during the comparison period to generate a comparison signal.
1 . An image sensor comprising:
a buffer circuit suitable for generating, based on at least one first signal, at least one second signal controlled during each of settling and comparison periods; and
a comparison circuit suitable for using an operating current having a relatively high level during the settling period and a relatively low level during the comparison period based on the second signal, and comparing a pixel signal with a ramp signal during the comparison period to generate a comparison signal,
wherein the buffer circuit includes:
a switch suitable for selectively transferring a bias voltage as a bias signal based on a switching control signal; and
an inverter suitable for inverting a source control signal and outputting a suppression control signal,
wherein the at least one first signal includes the switching control signal, the bias voltage and the source control signal, and
wherein the at least one second signal includes the bias signal and the suppression control signal.
2 . An image sensor comprising:
a buffer circuit suitable for generating, based on at least one first signal, at least one second signal controlled during each of settling and comparison periods; and
a comparison circuit suitable for using an operating current having a relatively high level during the settling period and a relatively low level during the comparison period based on the second signal, and comparing a pixel signal with a ramp signal during the comparison period to generate a comparison signal,
wherein the buffer circuit includes:
a first driver connected between a supply terminal of a high voltage and an output terminal of a bias signal, and suitable for receiving a first bias voltage;
a second driver connected between the output terminal of the bias signal and a supply terminal of a low voltage, and suitable for receiving a second bias voltage;
a first inverter suitable for inverting a source control signal to generate a suppression control signal;
a second inverter suitable for inverting the suppression control signal to generate a driving control signal;
a third driver connected to the output terminal of the bias signal, and suitable for receiving the driving control signal; and
a fourth driver connected between the third driver and the supply terminal of the low voltage, and suitable for receiving the second bias voltage,
wherein the at least one first signal includes the first bias voltage, the second bias voltage and the source control signal, and
wherein the at least one second signal includes the bias signal.
3 . The image sensor of claim 1 ,
wherein the comparison circuit includes:
a current sinking element connected between a common node and a supply terminal of a low voltage, and suitable for receiving a bias signal;
a first input element connected between the common node and an output terminal of the comparison signal, and suitable for receiving the pixel signal;
a second input element connected between the common node and an inverting output terminal, and suitable for receiving the ramp signal;
a first current source element connected between the output terminal and a supply terminal of a high voltage; and
a second current source element connected between the inverting output terminal and the supply terminal of the high voltage, and connected to the first current source element in a mirroring structure, and
wherein the at least one second signal includes the bias signal.
4 . The image sensor of claim 1 ,
wherein the comparison circuit includes:
a first current sinking element connected between a common node and a supply terminal of a low voltage, and suitable for receiving a bias signal;
a second current sinking element connected to the supply terminal of the low voltage, and suitable for receiving the bias signal;
a third current sinking element connected between the second current sinking element and the common node, and suitable for receiving the suppression control signal;
a first input element connected between the common node and an output terminal of the comparison signal, and suitable for receiving the pixel signal;
a second input element connected between the common node and an inverting output terminal, and suitable for receiving the ramp signal;
a first current source element connected between the output terminal and a supply terminal of a high voltage; and
a second current source element connected between the inverting output terminal and the supply terminal of the high voltage, and connected to the first current source element in a mirroring structure, and
wherein the at least one second signal includes the bias signal and the suppression control signal.
5 . The image sensor of claim 1 , further comprising a noise suppression circuit connected to an output terminal of the comparison signal, and suitable for suppressing noise, which is applied to the comparison signal during the comparison period, based on the suppression control signal.
6 . The image sensor of claim 5 , wherein the noise suppression circuit includes:
a switch connected to the output terminal, and suitable for switching based on the suppression control signal; and
a capacitor connected between the switch of the noise suppression circuit and a supply terminal of a low voltage.
7 . The image sensor of claim 5 , wherein the at least one second signal includes the suppression control signal.
8 . An image sensor comprising:
a comparison circuit suitable for comparing, based on a bias signal, a pixel signal with a ramp signal and outputting a comparison signal;
a noise suppression circuit connected to an output terminal of the comparison signal, and suitable for suppressing noise, which is applied to the comparison signal during a specific period, based on a suppression control signal;
a bias generation circuit suitable for generating a bias voltage; and
a buffer circuit suitable for generating the suppression control signal and the bias signal based on the bias voltage, a source control signal and a switching control signal.
9 . The image sensor of claim 8 , wherein the specific period includes at least one comparison period in which the ramp signal ramps.
10 . The image sensor of claim 8 , wherein the noise suppression circuit includes:
a switch connected to the output terminal, and suitable for switching based on the suppression control signal; and
a capacitor connected between the switch and a supply terminal of a low voltage.
11 . The image sensor of claim 8 , further comprising:
the bias generation circuit suitable for generating a first bias voltage and a second bias voltage; and
the buffer circuit suitable for generating the suppression control signal and the bias signal based on the first bias voltage, the second bias voltage and a source control signal.
12 . The image sensor of claim 11 , wherein the buffer circuit includes:
a first driver connected between a supply terminal of a high voltage and an output terminal of the bias signal, and suitable for receiving the first bias voltage;
a second driver connected between the output terminal of the bias signal and a supply terminal of a low voltage, and suitable for receiving the second bias voltage;
a first inverter suitable for inverting the source control signal to generate the suppression control signal;
a second inverter suitable for inverting the suppression control signal to generate a driving control signal;
a third driver connected to the output terminal of the bias signal, and suitable for receiving the driving control signal; and
a fourth driver connected between the third driver and the supply terminal of the low voltage, and suitable for receiving the second bias voltage.
13 . The image sensor of claim 11 , wherein the comparison circuit includes:
a current sinking element connected between a common node and a supply terminal of a low voltage, and suitable for receiving the bias signal;
a first input element connected between the common node and the output terminal, and suitable for receiving the pixel signal;
a second input element connected between the common node and an inverting output terminal, and suitable for receiving the ramp signal;
a first current source element connected between the output terminal and a supply terminal of a high voltage; and
a second current source element connected between the inverting output terminal and the supply terminal of the high voltage, and connected to the first current source element in a mirroring structure.
14 . The image sensor of claim 8 , wherein the buffer circuit includes:
a switch suitable for selectively transferring the bias voltage as the bias signal based on the switching control signal; and
an inverter suitable for inverting the source control signal and outputting the suppression control signal.
15 . The image sensor of claim 8 , wherein the comparison circuit includes:
a first current sinking element connected between a common node and a supply terminal of a low voltage, and suitable for receiving the bias signal;
a second current sinking element connected to the supply terminal of the low voltage, and suitable for receiving the bias signal;
a third current sinking element connected between the second current sinking element and the common node, and suitable for receiving the suppression control signal;
a first input element connected between the common node and the output terminal, and suitable for receiving the pixel signal;
a second input element connected between the common node and an inverting output terminal, and suitable for receiving the ramp signal;
a first current source element connected between the output terminal and a supply terminal of a high voltage; and
a second current source element connected between the inverting output terminal and the supply terminal of the high voltage, and connected to the first current source element in a mirroring structure.