Imaging device and electronic apparatus

Inventors: Gui Gui (Rochester, NY); Hirotaka Murakami (San Jose, CA); Hung Doan (Rochester, NY); Sungin Han (New York, NY); Frederick Brady (Rochester, NY)

Assignee: Sony Semiconductor Solutions Corporation

H04N25/77 H04N25/46

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Quick Facts

Patent No.: US 12684263
App. No.: 18/366,893
Granted: Jul 14, 2026
Kind: B2

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Abstract

Color image sensors and systems are provided. A color image sensor as disclosed includes a plurality of pixels disposed within an array, each of which includes a plurality of sub-pixels. A pixel array includes pixel cells, each pixel cell including one or more photodiodes. Pixel cells are arranged in rows and columns. The pixel array includes transistors for vertical binning of pixel cells in different rows and transistors for horizontal binning of pixel cells in different columns.

Claims (37)

1 . An image sensor, comprising:

a sensor substrate; and

a pixel array disposed in the sensor substrate, the pixel array including:

a plurality of pixel cells arranged in rows and columns, wherein a first pixel cell of the plurality of pixel cells outputs a first pixel signal, a second pixel cell of the plurality of pixel cells outputs a second pixel signal, a third pixel cell of the plurality of pixels cells outputs a third pixel signal, the first and second pixel cells are in different rows of the pixel array, the first and third pixel cells are in different columns of the pixel array, and each pixel cell includes a floating diffusion, a plurality of photoelectric conversion devices, and a row select transistor;

a first transistor to enable vertical binning, the first transistor coupled to a floating diffusion of the first pixel cell and a floating diffusion of the second pixel cell; and

a second transistor to enable horizontal binning, the second transistor coupled to the floating diffusion of the first pixel cell and a floating diffusion of the third pixel cell.

2 . The image sensor of claim 1 , wherein each pixel cell further includes a source follower transistor coupled to the floating diffusion and the row select transistor.

3 . The image sensor of claim 1 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to a second bitline, and the third pixel cell outputs the third pixel signal to a third bitline.

4 . The image sensor of claim 1 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to the first bitline, and the third pixel cell outputs the third pixel signal to a second bitline.

5 . The image sensor of claim 1 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to a second bitline, and the third pixel cell outputs the third pixel signal to the second bitline.

6 . The image sensor of claim 1 , wherein the first pixel cell outputs the first pixel signal and the second pixel cell outputs the second pixel signal in response to a common selection signal.

7 . The image sensor of claim 1 , wherein the first pixel cell outputs the first pixel signal and the third pixel cell outputs the third pixel signal in response to a common selection signal.

8 . An imaging system, comprising:

a substrate;

a pixel array disposed in the substrate, the pixel array including:

a plurality of pixel cells arranged in rows and columns, wherein a first pixel cell of the plurality of pixel cells outputs a first pixel signal, a second pixel cell of the plurality of pixel cells outputs a second pixel signal, a third pixel cell of the plurality of pixel cells outputs a third pixel signal, the first and second pixel cells are in different rows of the pixel array, the first and third pixel cells are in different columns of the pixel array, and each pixel cell includes a floating diffusion, a plurality of photoelectric conversion devices, and a row select transistor;

a first transistor to enable vertical binning, the first transistor coupled to a floating diffusion of the first pixel cell and a floating diffusion of the second pixel cell; and

a second transistor to enable horizontal binning, the second transistor coupled to the floating diffusion of the first pixel cell and a floating diffusion of the third pixel cell; and

readout circuitry coupled to the pixel array to readout image data from the pixel array.

9 . The imaging system of claim 8 , wherein each pixel cell further includes a source follower transistor coupled to the floating diffusion and the row select transistor.

10 . The imaging system of claim 8 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to a second bitline, and the third pixel cell outputs the third pixel signal to a third bitline.

11 . The imaging system of claim 8 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to the first bitline, and the third pixel cell outputs the third pixel signal to a second bitline.

12 . The imaging system of claim 8 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to a second bitline, and the third pixel cell outputs the third pixel signal to the second bitline.

13 . The imaging system of claim 8 , wherein the first pixel cell outputs the first pixel signal and the second pixel cell outputs the second pixel signal in response to a common selection signal.

14 . The imaging system of claim 8 , wherein the first pixel cell outputs the first pixel signal and the third pixel cell outputs the third pixel signal in response to a common selection signal.

15 . An imaging system, comprising:

a sensor substrate;

a pixel array disposed in the sensor substrate, the pixel array including:

a plurality of pixel cells arranged in rows and columns, wherein a first pixel cell of the plurality of pixel cells outputs a first pixel signal, a second pixel cell of the plurality of pixel cells outputs a second pixel signal, a third pixel cell of the plurality of pixel cells outputs a third pixel signal, the first and second pixel cells are in different rows of the pixel array, the first and third pixel cells are in different columns of the pixel array, and each pixel cell includes a floating diffusion, a plurality of photoelectric conversion devices, and a row select transistor;

a first transistor to enable vertical binning, the first transistor coupled to a floating diffusion of the first pixel cell of the plurality of pixel cells and a floating diffusion of the second pixel cell of the plurality of pixel cells; and

a second transistor to enable horizontal binning, the second transistor coupled to the floating diffusion of the first pixel cell and a floating diffusion of the third pixel cell of the plurality of pixel cells; and

one or more lenses.

16 . The imaging system of claim 15 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to a second bitline, and the third pixel cell outputs the third pixel signal to a third bitline.

17 . The imaging system of claim 15 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to the first bitline, and the third pixel cell outputs the third pixel signal to a second bitline.

18 . The imaging system of claim 15 , wherein the first pixel cell outputs the first pixel signal to a first bitline, the second pixel cell outputs the second pixel signal to a second bitline, and the third pixel cell outputs the third pixel signal to the second bitline.

19 . The imaging system of claim 15 , wherein the first pixel cell outputs the first pixel signal and the second pixel cell outputs the second pixel signal in response to a common selection signal.

20 . The imaging system of claim 15 , wherein the first pixel cell outputs the first pixel signal and the third pixel cell outputs the third pixel signal in response to a common selection signal.