Static random access memory including three-dimensional diodes

1 . A static random access memory, comprising:

a substrate, comprising a first fin, a second fin, a third fin, and a fourth fin; and

a first memory cell, comprising:

a first pull-down transistor, disposed on a first segment of the first fin;

a first pull-up transistor, disposed on a first segment of the second fin;

a second pull-up transistor, disposed on a first segment of the third fin;

a second pull-down transistor, disposed on a first segment of the fourth fin;

a first diode, comprising a first conductive feature in contact with a top surface and a plurality of upper sidewalls of a first end of the first segment of the first fin; and

a second diode, comprising a second conductive feature in contact with a top surface and a plurality of upper sidewalls of a second end of the first segment of the fourth fin.

2 . The static random access memory of claim 1 , wherein the first diode is landed on a first diffusion break structure.

3 . The static random access memory of claim 2 , further comprising a second memory cell, wherein the first diffusion break structure is located between the first memory cell and the second memory cell.

4 . The static random access memory of claim 3 , wherein the first conductive feature is further in contact with a top surface and a plurality of upper sidewalls of a first end of a second segment of the first fin.

5 . The static random access memory of claim 4 , wherein the first conductive feature comprises a first metal contact and a first barrier layer, and the first metal contact is located on the first barrier layer.

6 . The static random access memory of claim 4 , wherein the first diffusion break structure separates the first segment from the second segment of the first fin, separates the first segment from a second segment of the second fin, separates the first segment from a second segment of the third fin second segment, and separates the first segment from a second segment of the fourth fin.

7 . The static random access memory of claim 1 , wherein the second diode is landed on a second diffusion break structure.

8 . The static random access memory of claim 7 , wherein the second diffusion break structure is in contact with a second end of the first segment of the first fin, and is in contact with a second end of the first segment of the fourth fin.

9 . The static random access memory of claim 7 , wherein the second conductive feature comprises a second metal contact and a second barrier layer, and the second metal contact is located on the second barrier layer.

10 . The static random access memory of claim 7 , further comprising a third memory cell, wherein the second diffusion break structure is located between the first memory cell and the third memory cell.

11 . The static random access memory of claim 1 , wherein first cross-sections of the first conductive feature and the second conductive feature are T-shaped, respectively.

12 . The static random access memory of claim 1 , wherein second cross-sections of the first conductive feature and the second conductive feature are inverted U-shaped, respectively.

13 . The static random access memory of claim 1 , wherein the first diode and the second diode are three-dimensional Schottky barrier diodes.

14 . A static random access memory, comprising:

a semiconductor substrate;

a plurality of transistors, disposed on the semiconductor substrate;

a first three-dimensional diode, comprising a first conductive feature located on a top surface of the semiconductor substrate and extending into the semiconductor substrate; and

a second three-dimensional diode, comprising a second conductive feature located on the top surface of the semiconductor substrate and extending into the semiconductor substrate,

wherein the first conductive feature is in contact with a top surface and a plurality of sidewalls of a first semiconductor fin of the semiconductor substrate, and the second conductive feature is in contact with a top surface and a plurality of sidewalls of a second semiconductor fin of the semiconductor substrate.

15 . The static random access memory of claim 14 , wherein the first three-dimensional diode is shared by a first memory cell and a second memory cell adjacent to each other, and the second three-dimensional diode is shared by the first memory cell and a third memory cell adjacent to each other.

16 . The static random access memory of claim 15 , wherein the first three-dimensional diode is located between two first pull-down transistors of two adjacent memory cells, and the second three-dimensional diode is located between two second pull-down transistors of two adjacent memory cells.

17 . The static random access memory of claim 14 , wherein the first three-dimensional diode is landed on a first diffusion break structure, and the second three-dimensional diode is landed on a second diffusion break structure.

18 . The static random access memory of claim 14 , wherein the first conductive feature comprises a first metal contact and a first barrier layer, the first metal contact is located on the first barrier layer, the second conductive feature comprises a second metal contact and a second barrier layer, and the second metal contact is located on the second barrier layer.

19 . The static random access memory of claim 14 , wherein first cross-sections of the first conductive feature and the second conductive feature are T-shaped, respectively, and second cross-sections of the first conductive feature and the second conductive feature are inverted U-shaped, respectively.