3-D DRAM structures and methods of manufacture
Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.
1 . A memory device comprising:
a plurality of active regions separated and spaced along a first direction, a second direction, and a third direction;
a plurality of conductive layers arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction;
a conductive bridge extending along the second direction and connecting each conductive layer to one or more adjacent conductive layers, the conductive bridge having a length along the first direction that is smaller than the length of each of the plurality of conductive layers along the first direction;
a gate oxide layer between the plurality of active regions and the at least one conductive layer;
a capacitor on a first side of the plurality of active regions along the first direction, the capacitor not in direct contact with the plurality of conductive layers or with the conductive bridge, the capacitor including a first electrode in contact with a doped layer, a high-k dielectric disposed inside the first electrode and a second electrode disposed inside the high-k dielectric, the first electrode extending in the first direction so as to cover the high-k dielectric, the high-k dielectric extending in the first direction so as to cover the second electrode, and the second electrode extending in the first direction so as to cover a dielectric;
the doped layer between the capacitor and the plurality of active regions in the first direction; and
a source/drain region on a second side of the plurality of active regions along the first direction, the second side opposite the first side.
2 . The memory device of claim 1 , wherein the plurality of active regions comprise a transistor.
3 . The memory device of claim 1 , further comprising a bit line extending along the third direction adjacent the active regions spaced along the third direction.
4 . The memory device of claim 1 , wherein each of the plurality of active regions comprises a transistor and a gate is between the transistor and the conductive layers along the third direction, wherein each active region is in connection with a single gate.
5 . A memory device comprising:
a plurality of pairs of active regions, the pairs spaced along a first direction, a second direction and a third direction;
a plurality of bit lines extending along the third direction between pairs of active regions spaced in the first direction;
a plurality of conductive layers arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions, the at least one side being located along the third direction relative to the plurality of pairs of active regions;
a conductive bridge extending along the second direction connecting each conductive layer to one or more adjacent conductive layers, the conductive bridge having a bridge length along the first direction that is smaller than a conductive layer length of each of the plurality of conductive layers along the first direction;
a gate oxide layer between the plurality of pairs of active regions and the plurality of conductive layers in the third direction;
a capacitor on one side of the plurality of pairs of active regions opposite the plurality of bit lines in the first direction, the capacitor including a first electrode in contact with a doped layer, a high-k dielectric disposed inside the first electrode and a second electrode disposed inside the high-k dielectric, the first electrode extending in the first direction so as to cover the high-k dielectric, the high-k dielectric extending in the first direction so as to cover the second electrode, and the second electrode extending in the first direction so as to cover a dielectric;
the doped layer between the capacitor and the plurality of pairs of active regions in the first direction; and
a source/drain region on another side of the plurality of pairs of active regions adjacent to the plurality of bit lines in the first direction are provided with each of the active regions.
6 . The memory device of claim 5 , wherein the plurality of pairs of active regions comprises a transistor and a gate is between the transistor and the conductive layers along the third direction.
7 . The memory device of claim 6 , wherein the conductive layer length along the first direction is in the range of 50 nm to 300 nm, and the bridge length along the first direction is in the range of 5 nm to 180 nm.
8 . The memory device of claim 6 , wherein each of the plurality of pairs of active regions is in connection with a single gate.