Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate including a cell array region and a core region disposed around the cell array region; a plurality of storage element contacts; a contact plug; and a contact plug spacer. The plurality of storage element contacts may include a first storage element contact and at least one second storage element contact, the first storage element contact is a closest storage element contact of the plurality of storage element contacts to the core region, such that the first storage element contact is between the core region and the at least one second storage element contact. A step difference in a vertical direction perpendicular to the substrate between a top surface of the first storage element contact and a top surface of the at least one second storage element contact is 5 nm or less.
1 . A method of manufacturing a semiconductor device, the method comprising:
forming a first insulating layer in a cell array region of a substrate, the substrate including the cell array region and a core region;
etching the first insulating layer to form a plurality of storage element contact holes;
filling at least a portion of the plurality of storage element contact holes, forming a dummy mold layer over the core region and the cell array region, and planarizing the dummy mold layer to expose a top surface of the first insulating layer and form a dummy mold pattern in the plurality of storage element contact holes;
forming a contact plug hole in the core region; and
forming a contact plug spacer on an inner wall of the contact plug hole.
2 . The method of claim 1 , wherein the forming of the dummy mold pattern includes planarizing the dummy mold layer so that a top surface of the core region and a top surface of the cell array region are positioned on a same level.
3 . The method of claim 1 , wherein a plurality of cell line structures is formed in the cell array region, and an insulating layer configured to form a fence is formed as the first insulating layer between the plurality of cell line structures.
4 . The method of claim 3 , further comprising:
forming a cell spacer covering the plurality of cell line structures prior to forming the dummy mold pattern,
wherein the contact plug spacer is formed to be thicker than the cell spacer.
5 . The method of claim 1 , wherein a plurality of first conductive lines is formed in the cell array region, and an upper insulating layer is formed as the first insulating layer on the plurality of first conductive lines.
6 . The method of claim 1 , further comprising:
forming a plurality of core gate structures in the core region;
forming a buried insulating layer between the plurality of core gate structures; and
forming a mask layer on the plurality of core gate structures and the buried insulating layer,
wherein the contact plug hole is formed based on penetrating the mask layer and the buried insulating layer.
7 . The method of claim 6 , wherein:
the plurality of core gate structures includes a core gate electrode, a core gate capping pattern on the core gate electrode, and a core gate spacer on a sidewall of the core gate electrode and on a sidewall of the core gate capping pattern, and
the contact plug hole is formed based on penetrating the mask layer and the buried insulating layer and partially passing through the core gate spacer.