Semiconductor device with an electrically conductive structure having a capping layer sidewall directly contacting a contact structure and manufacturing method thereof

1 . A semiconductor device, comprising:

a semiconductor substrate having a cell region and a peripheral region, wherein the semiconductor substrate comprises at least one fin-shaped structure isolated by an insulation structure;

a first stacked structure disposed in the semiconductor substrate, wherein the first stacked structure is disposed straddling the at least one fin-shaped structure, extends in a horizontal direction, and is disposed in the cell region and the peripheral region, and the first stacked structure comprises:

an electrically conductive layer comprising:

a first portion located in the cell region; and

a second portion located in the peripheral region;

a capping layer disposed on the electrically conductive layer; and

a dielectric capping layer disposed on the capping layer and the electrically conductive layer, wherein the dielectric capping layer contacts a top surface of the second portion of the electrically conductive layer; and

a contact structure directly contacting the electrically conductive layer and electrically connected with the first stacked structure,

wherein a sidewall of the capping layer faces the contact structure in the horizontal direction, and the contact structure directly contacts the sidewall of the capping layer.

2 . The semiconductor device according to claim 1 , wherein at least a part of the top surface of the second portion of the electrically conductive layer is not covered by the capping layer.

3 . The semiconductor device according to claim 1 , wherein a first bottom surface of the contact structure is located between the capping layer and a second bottom surface of the contact structure in the horizontal direction, and the second bottom surface is lower than the first bottom surface in a vertical direction.

4 . The semiconductor device according to claim 1 , wherein the dielectric capping layer directly contacts a top surface of the electrically conductive layer and a top surface of the capping layer.

5 . The semiconductor device according to claim 1 , further comprising:

a second stacked structure disposed above the semiconductor substrate, wherein the second stacked structure is located on the cell region, the second stacked structure is disposed adjacent to an interface between the cell region and the peripheral region, and a distance between the sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the second stacked structure and the contact structure in the horizontal direction.

6 . The semiconductor device according to claim 1 , wherein the electrically conductive layer comprises a metallic electrically conductive material, and the capping layer comprises doped polycrystalline silicon or undoped polycrystalline silicon.

7 . The semiconductor device according to claim 1 , further comprising:

a mask layer disposed on the first stacked structure, wherein the mask layer is partially located on the peripheral region, and the contact structure penetrates through the mask layer.

8 . The semiconductor device according to claim 1 , wherein a distance between the sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the at least one fin-shaped structure and the contact structure in the horizontal direction.

9 . A manufacturing method of a semiconductor device, comprising:

providing a semiconductor substrate having a cell region and a peripheral region, wherein the semiconductor substrate comprises at least one fin-shaped structure isolated by an insulation structure;

forming a first stacked structure in the semiconductor substrate, wherein the first stacked structure is formed straddling the at least one fin-shaped structure, extends in a horizontal direction, and is formed in the cell region and the peripheral region, and the first stacked structure comprises:

an electrically conductive layer comprising:

a first portion located in the cell region; and

a second portion located in the peripheral region;

a capping layer disposed on the electrically conductive layer; and

a dielectric capping layer disposed on the capping layer and the electrically conductive layer, wherein the dielectric capping layer contacts a top surface of the second portion of the electrically conductive layer; and

forming a contact structure, wherein the contact structure directly contacts the electrically conductive layer and is electrically connected with the first stacked structure, a sidewall of the capping layer faces the contact structure in the horizontal direction, and the contact structure directly contacts the sidewall of the capping layer.

10 . The manufacturing method of the semiconductor device according to claim 9 , wherein a method of forming the first stacked structure comprises:

forming a trench in the semiconductor substrate, wherein the trench is partly located in the cell region and partly located in the peripheral region;

forming the electrically conductive layer in the trench;

forming the capping layer on the electrically conductive layer; and

removing a part of the capping layer for exposing the top surface of the second portion of the electrically conductive layer.

11 . The manufacturing method of the semiconductor device according to claim 10 , wherein the method of forming the first stacked structure further comprises:

forming the dielectric capping layer in the trench after the part of the capping layer is removed.

12 . The manufacturing method of the semiconductor device according to claim 11 , wherein the sidewall of the capping layer is located above the second portion of the electrically conductive layer after the part of the capping layer is removed.

13 . The manufacturing method of the semiconductor device according to claim 9 , further comprising:

forming a second stacked structure above the semiconductor substrate after the first stacked structure is formed, wherein the second stacked structure is located on the cell region, the second stacked structure is disposed adjacent to an interface between the cell region and the peripheral region, and a distance between the sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the second stacked structure and the contact structure in the horizontal direction.

14 . A semiconductor device, comprising:

a semiconductor substrate having a cell region and a peripheral region, wherein the semiconductor substrate comprises at least one fin-shaped structure isolated by an insulation structure;

a first stacked structure disposed in the semiconductor substrate, wherein the first stacked structure is disposed straddling the at least one fin-shaped structure, extends in a horizontal direction, and is disposed in the cell region and the peripheral region, and the first stacked structure comprises:

an electrically conductive layer comprising:

a first portion located in the cell region; and

a second portion located in the peripheral region;

a capping layer disposed on the electrically conductive layer; and

a dielectric capping layer disposed on the capping layer and the electrically conductive layer, wherein the dielectric capping layer contacts a top surface of the second portion of the electrically conductive layer; and

a contact structure directly contacting the electrically conductive layer and electrically connected with the first stacked structure,

wherein the contact structure further contacts the capping layer directly, a first bottom surface of the contact structure is located between the capping layer and a second bottom surface of the contact structure in the horizontal direction, and the second bottom surface is lower than the first bottom surface in a vertical direction.

15 . The semiconductor device according to claim 14 , wherein at least a part of the top surface of the second portion of the electrically conductive layer is not covered by the capping layer.

16 . The semiconductor device according to claim 14 , wherein a sidewall of the capping layer faces the contact structure in the horizontal direction, and the contact structure directly contacts the sidewall of the capping layer.

17 . The semiconductor device according to claim 14 , wherein the dielectric capping layer directly contacts a top surface of the electrically conductive layer and a top surface of the capping layer.

18 . The semiconductor device according to claim 14 , further comprising:

a second stacked structure disposed above the semiconductor substrate, wherein the second stacked structure is located on the cell region, the second stacked structure is disposed adjacent to an interface between the cell region and the peripheral region, and a distance between a sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the second stacked structure and the contact structure in the horizontal direction.

19 . The semiconductor device according to claim 14 , wherein the electrically conductive layer comprises a metallic electrically conductive material, and the capping layer comprises doped polycrystalline silicon or undoped polycrystalline silicon.

20 . The semiconductor device according to claim 14 , wherein a sidewall of the capping layer faces the contact structure in the horizontal direction, and a distance between the sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the at least one fin-shaped structure and the contact structure in the horizontal direction.