Semiconductor devices including conductive pattern on channel
A semiconductor device may include a bit line on a substrate, a gate electrode over the bit line and spaced apart from the bit line, a gate insulation pattern on a sidewall of the gate electrode, a channel on a sidewall of the gate insulation pattern and including an oxide semiconductor material, a conductive pattern contacting an upper surface of the channel and including an amorphous oxide semiconductor material, and a contact plug contacting an upper surface of the conductive pattern. The contact plug may include a metal. The amorphous oxide semiconductor material may include fluorine (F), chlorine (Cl), nitrogen (N), hydrogen (H), or argon (Ar).
1 . A semiconductor device comprising:
a bit line on a substrate;
a gate electrode over the bit line and spaced apart from the bit line;
a gate insulation pattern on a sidewall of the gate electrode;
a channel on a sidewall of the gate insulation pattern, the channel including an oxide semiconductor material;
a conductive pattern contacting an upper surface of the channel,
the conductive pattern including an amorphous oxide semiconductor material,
the amorphous oxide semiconductor material including fluorine (F), chlorine (Cl), nitrogen (N), hydrogen (H) or argon (Ar); and
a contact plug contacting an upper surface of the conductive pattern,
the contact plug including a metal.
2 . The semiconductor device according to claim 1 , wherein
a lower surface of the conductive pattern is lower than an upper surface of the gate electrode,
the conductive pattern overlaps a portion of the gate electrode in a horizontal direction, and
the horizontal direction is parallel to an upper surface of the substrate.
3 . The semiconductor device according to claim 1 , wherein the channel includes an amorphous oxide semiconductor material.
4 . The semiconductor device according to claim 1 , wherein the gate insulation pattern includes a metal oxide.
5 . The semiconductor device according to claim 1 , wherein
a cross-section of the gate insulation pattern in a vertical direction has an “L” shape, and
the vertical direction is perpendicular to an upper surface of the substrate.
6 . The semiconductor device according to claim 1 , wherein the upper surface of the conductive pattern is coplanar with an upper surface of the gate insulation pattern.
7 . The semiconductor device according to claim 1 , further comprising:
a capacitor on the contact plug.
8 . The semiconductor device according to claim 1 , further comprising:
an insulation pattern between an upper surface of the gate electrode and a lower surface of the contact plug, wherein
the insulation pattern includes an insulating nitride.
9 . The semiconductor device according to claim 1 , wherein
a cross-section of the channel in a vertical direction has a cup shape, and
the vertical direction is perpendicular to an upper surface of the substrate.
10 . A semiconductor device comprising:
bit lines on a substrate, each of the bit lines extending in a first direction, the first direction being parallel to an upper surface of the substrate, the bit lines being spaced apart from each other in a second direction, the second direction being parallel to the upper surface of the substrate and the second direction crossing the first direction;
gate electrodes spaced apart from each other in the first direction on the bit lines, each of the gate electrodes extending in the second direction;
a gate insulation pattern on a sidewall in the first direction of each of the gate electrodes;
a channel on a sidewall in the first direction of the gate insulation pattern, the channel including an oxide semiconductor material;
a conductive pattern on the channel; and
a contact plug on the conductive pattern, the contact plug including a metal, wherein
a conductive material of the conductive pattern is different from the metal of the contact plug, and
the conductive pattern overlaps a portion of a corresponding one of the gate electrodes in the first direction such that a distance from a lower surface of the conductive pattern to the upper surface of the substrate is less than a distance from an upper surface of the corresponding one of the gate electrodes to the upper surface of the substrate, and the distance from the lower surface of the conductive pattern to the upper surface of the substrate is greater than a distance from a lower surface of the corresponding one of the gate electrodes to the upper surface of the substrate.
11 . The semiconductor device according to claim 10 , wherein
the conductive pattern includes an amorphous oxide semiconductor material, and
the amorphous oxide semiconductor material includes fluorine (F), chlorine (Cl), nitrogen (N), hydrogen (H) or argon (Ar).
12 . The semiconductor device according to claim 11 , wherein an upper surface of the channel contacts the lower surface of the conductive pattern.
13 . The semiconductor device according to claim 10 , wherein an upper surface of the conductive pattern contacts a lower surface of the contact plug.
14 . The semiconductor device according to claim 10 , further comprising:
an insulation pattern between an upper surface of each of the gate electrodes and a lower surface of the contact plug, wherein
the insulation pattern includes an insulating nitride.
15 . The semiconductor device according to claim 10 , wherein a cross-section of the channel in the first direction has a cup shape.
16 . A semiconductor device comprising:
bit lines on a substrate, each of the bit lines extending in a first direction, the first direction parallel to an upper surface of the substrate, and the bit lines being spaced apart from each other in a second direction, the second direction being parallel to the upper surface of the substrate and the second direction crossing the first direction;
gate electrodes spaced apart from each other in the first direction on the bit lines, each of the gate electrodes extending in the second direction;
a gate insulation pattern on a sidewall in the first direction of each of the gate electrodes;
a channel on a sidewall in the first direction of the gate insulation pattern, the channel including an oxide semiconductor material;
a conductive pattern on the channel,
the conductive pattern including an amorphous oxide semiconductor material,
the amorphous oxide semiconductor material including fluorine (F), chlorine (Cl), nitrogen (N), hydrogen (H) or argon (Ar);
a contact plug on the conductive pattern, the contact plug including a metal; and
a capacitor on the contact plug.
17 . The semiconductor device according to claim 16 , wherein
an upper surface of the channel contacts a lower surface of the conductive pattern, and an upper surface of the conductive pattern contacts a lower surface of the contact plug.
18 . The semiconductor device according to claim 16 , wherein
a lower surface of the conductive pattern is lower than an upper surface of each of the gate electrodes,
the conductive pattern overlaps a portion of each of the gate electrodes in a horizontal direction, and
the horizontal direction is parallel to the upper surface of the substrate.
19 . The semiconductor device according to claim 16 , further comprising:
an insulation pattern between an upper surface of each of the gate electrodes and a lower surface of the contact plug, wherein
the insulation pattern includes an insulating nitride.
20 . The semiconductor device according to claim 16 , wherein
a cross-section of the channel in a vertical direction has a cup shape, and
the vertical direction is perpendicular to the upper surface of the substrate.