IP Library Granted Patent US 12684764
Granted Patent B2
US 12684764 · App. 18/154,870 · Granted Jul 14, 2026

Semiconductor device and method of manufacturing the same

Inventors: Mei-Yuan Chou (Taichung City, TW); Yoshinori Tanaka (Taichung City, TW)
Assignee: Winbond Electronics Corp.
H10B12/50H10B12/09H10B12/315H10B12/34
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Quick Facts
Patent No.
US 12684764
App. No.
18/154,870
Granted
Jul 14, 2026
Kind
B2
Abstract

A semiconductor device, including a first MOS device, a second MOS device, a first dielectric layer, a stop layer, and a second dielectric layer, is provided. The first MOS device and the second MOS device are located on a substrate. The first dielectric layer is beside the first MOS device and the second MOS device. The stop layer is disposed on the first dielectric layer. The second dielectric layer covers the stop layer. The thickness of the second dielectric layer above the first MOS device is greater than the thickness of the second dielectric layer above the second MOS device.

Claims (18)

1 . A semiconductor device, comprising:

a first MOS device located on a substrate;

a second MOS device located on the substrate;

a first dielectric layer completely filling a space between the first MOS device and the second MOS device;

a stop layer disposed on a top surface of the first dielectric layer and the second MOS device; and

a second dielectric layer covering the stop layer, wherein a thickness of the second dielectric layer above the first MOS device is greater than a thickness of the second dielectric layer above the second MOS device,

wherein the second dielectric layer is not in contact with the second MOS device and is in direct contact with the first MOS device.

2 . The semiconductor device according to claim 1 , wherein the second dielectric layer extends through the stop layer to be in contact with the first MOS device.

3 . The semiconductor device according to claim 2 , wherein the first MOS device comprises an N-channel MOS device, and the second MOS device comprises a P-channel MOS device.

4 . A semiconductor device, comprising:

a first MOS device located on a substrate;

a second MOS device located on the substrate;

a first dielectric layer completely filling a space between the first MOS device and the second MOS device;

a first stop layer disposed on a top surface of the first dielectric layer and the second MOS device; and

a second stop layer disposed on the first stop layer, wherein a thickness of the second stop layer above the first MOS device is greater than a thickness of the second stop layer above the second MOS device,

wherein the second stop layer is in direct contact with a top surface of the first stop layer.

5 . The semiconductor device according to claim 4 , wherein the second stop layer is in contact with the first MOS device.

6 . The semiconductor device according to claim 4 , wherein a thickness of the first stop layer between the second stop layer and the first MOS device is less than a thickness of the first stop layer between the second stop layer and the second MOS device.