Semiconductor device
View Patent ↗A semiconductor device that can be subjected to multipoint measurement is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a first multiplexer, a second multiplexer, m (m is an integer of 1 or more) analog switches electrically connected to the first multiplexer, and n (n is an integer of 1 or more) analog switches electrically connected to the second multiplexer. The second layer includes m×n transistors. Each of the m analog switches is electrically connected to n transistors, and each of the n analog switches is electrically connected to m transistors.
1 . A semiconductor device comprising a first layer, a second layer over the first layer, a first wiring, a second wiring, and a third wiring,
wherein the first layer comprises a first multiplexer, a second multiplexer, and first to fourth analog switches,
wherein the second layer comprises first to fourth transistors,
wherein each of the first to fourth transistors comprises a source, a drain, and a first gate,
wherein the first wiring is electrically connected to one of the source and the drain of each of the first to fourth transistors,
wherein a first terminal of each of the first analog switch and the second analog switch is electrically connected to the first multiplexer,
wherein a second terminal of each of the first analog switch and the second analog switch is electrically connected to the second wiring,
wherein a third terminal of the first analog switch is electrically connected to the other of the source and the drain of each of the first transistor and the second transistor,
wherein a third terminal of the second analog switch is electrically connected to the other of the source and the drain of each of the third transistor and the fourth transistor,
wherein a first terminal of each of the third analog switch and the fourth analog switch is electrically connected to the second multiplexer,
wherein a second terminal of each of the third analog switch and the fourth analog switch is electrically connected to the third wiring,
wherein a third terminal of the third analog switch is electrically connected to the first gate of each of the first transistor and the third transistor, and
wherein a third terminal of the fourth analog switch is electrically connected to the first gate of each of the second transistor and the fourth transistor.
2 . The semiconductor device according to claim 1 ,
further comprising a fourth wiring,
wherein each of the first to fourth transistors further comprises a second gate, and
wherein the fourth wiring is electrically connected to the second gate of each of the first to fourth transistors.
3 . The semiconductor device according to claim 1 ,
wherein each of the first to fourth transistors comprises a metal oxide in a channel formation region.
4 . The semiconductor device according to claim 3 ,
wherein the metal oxide comprises indium, gallium, and zinc.
5 . The semiconductor device according to claim 1 ,
wherein each of the first to fourth analog switches comprises a CMOS circuit.
6 . The semiconductor device according to claim 5 ,
wherein a transistor included in the CMOS circuit comprises silicon in a channel formation region.
7 . A semiconductor device comprising a first layer, a second layer over the first layer, a first wiring, a second wiring, and a third wiring,
wherein the first layer comprises a first multiplexer, a second multiplexer, and first to third analog switches,
wherein the second layer comprises a first transistor and a third transistor,
wherein each of the first transistor and the third transistor comprises a source, a drain, and a first gate,
wherein the first wiring is electrically connected to one of the source and the drain of each of the first transistor and the third transistor,
wherein a first terminal of each of the first analog switch and the second analog switch is electrically connected to the first multiplexer,
wherein a second terminal of each of the first analog switch and the second analog switch is electrically connected to the second wiring,
wherein a third terminal of the first analog switch is electrically connected to the other of the source and the drain of the first transistor,
wherein a third terminal of the second analog switch is electrically connected to the other of the source and the drain of the third transistor,
wherein a first terminal of the third analog switch is electrically connected to the second multiplexer,
wherein a second terminal of the third analog switch is electrically connected to the third wiring, and
wherein a third terminal of the third analog switch is electrically connected to the first gate of each of the first transistor and the third transistor.
8 . The semiconductor device according to claim 7 ,
further comprising a fourth wiring,
wherein each of the first transistor and the third transistor further comprises a second gate, and
wherein the fourth wiring is electrically connected to the second gate of each of the first transistor and the third transistor.
9 . The semiconductor device according to claim 7 ,
wherein each of the first transistor and the third transistor comprises a metal oxide in a channel formation region.
10 . The semiconductor device according to claim 9 ,
wherein the metal oxide comprises indium, gallium, and zinc.
11 . The semiconductor device according to claim 7 ,
wherein each of the first to third analog switches comprises a CMOS circuit.
12 . The semiconductor device according to claim 11 ,
wherein a transistor included in the CMOS circuit comprises silicon in a channel formation region.
13 . A semiconductor device comprising a first layer, a second layer over the first layer, a first wiring, a second wiring, and a third wiring,
wherein the first layer comprises a first multiplexer, a second multiplexer, a first analog switch, a third analog switch, and a fourth analog switch,
wherein the second layer comprises a first transistor and a second transistor,
wherein each of the first transistor and the second transistor comprises a source, a drain, and a first gate,
wherein the first wiring is electrically connected to one of the source and the drain of each of the first transistor and the second transistor,
wherein a first terminal of the first analog switch is electrically connected to the first multiplexer,
wherein a second terminal of the first analog switch is electrically connected to the second wiring,
wherein a third terminal of the first analog switch is electrically connected to the other of the source and the drain of each of the first transistor and the second transistor,
wherein a first terminal of each of the third analog switch and the fourth analog switch is electrically connected to the second multiplexer,
wherein a second terminal of each of the third analog switch and the fourth analog switch is electrically connected to the third wiring,
wherein a third terminal of the third analog switch is electrically connected to the first gate of the first transistor, and
wherein a third terminal of the fourth analog switch is electrically connected to the first gate of the second transistor.
14 . The semiconductor device according to claim 13 ,
further comprising a fourth wiring,
wherein each of the first transistor and the second transistor further comprises a second gate, and
wherein the fourth wiring is electrically connected to the second gate of each of the first transistor and the second transistor.
15 . The semiconductor device according to claim 13 ,
wherein each of the first transistor and the second transistor comprises a metal oxide in a channel formation region.
16 . The semiconductor device according to claim 15 ,
wherein the metal oxide comprises indium, gallium, and zinc.
17 . The semiconductor device according to claim 13 ,
wherein each of the first analog switch, the third analog switch, and the fourth analog switch comprises a CMOS circuit.
18 . The semiconductor device according to claim 17 ,
wherein a transistor included in the CMOS circuit comprises silicon in a channel formation region.