Semiconductor device with staircase gate stack and sidewall isolation structure

1 . A semiconductor device, comprising:

a memory stack of gate layers and insulating layers, the gate layers and the insulating layers being stacked alternatingly and being formed into stair steps in a staircase region;

a first landing pad on a first gate layer of a first stair step, the first gate layer being a top gate layer of the first stair step; and

a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step, the second gate layer being a top gate layer of the second stair step and being stacked on the first gate layer in the memory stack, the first sidewall isolation structure isolating the second gate layer from the first landing pad, wherein

the first sidewall isolation structure is in direct contact with the second gate layer and the first landing pad,

the first landing pad has a recessed area having a sidewall structure that is in direct contact with the first sidewall isolation structure, and

the recessed area is filled with a dielectric material.

2 . The semiconductor device of claim 1 , further comprising:

a second landing pad on the second gate layer of the second stair step, a sidewall of the second landing pad being covered by a different isolation layer from the first sidewall isolation structure.

3 . The semiconductor device of claim 2 , wherein the different isolation layer is a contact isolation layer in the staircase region, the contact isolation layer covers the first landing pad and the second landing pad.

4 . The semiconductor device of claim 3 , further comprising:

a first contact structure extending through the contact isolation layer and being connected with the first gate layer of the first stair step; and

a second contact structure extending through the contact isolation layer and being connected with the second gate layer of the second stair step.

5 . The semiconductor device of claim 3 , wherein the first sidewall isolation structure and the contact isolation layer are of different material properties.

6 . The semiconductor device of claim 5 , wherein the first sidewall isolation structure is formed of atomic layer deposition (ALD) silicon dioxide, and the contact isolation layer is formed of high density plasma silicon dioxide.

7 . The semiconductor device of claim 1 , further comprising:

a second sidewall isolation structure on a sidewall of multiple gate layers and insulating layers in the memory stack.

8 . The semiconductor device of claim 7 , wherein a width of the first sidewall isolation structure and the second sidewall isolation structure is in a range of 1 nm to 500 nm.

9 . The semiconductor device of claim 7 , further comprising:

a silicon nitride material on the second sidewall isolation structure.

10 . The semiconductor device of claim 1 , wherein the recessed area comprises an isotropic recess.

11 . The semiconductor device of claim 1 , wherein the sidewall structure is curved or beveled.

12 . The semiconductor device of claim 2 , further comprising:

a second sidewall isolation structure on a sidewall of multiple gate layers and insulating layers in the memory stack.

13 . The semiconductor device of claim 12 , wherein a width of the first sidewall isolation structure and the second sidewall isolation structure is in a range of 1 nm to 500 nm.

14 . The semiconductor device of claim 12 , further comprising:

a silicon nitride material on the second sidewall isolation structure.

15 . The semiconductor device of claim 2 , wherein the recessed area comprises an isotropic recess.

16 . The semiconductor device of claim 2 , wherein the sidewall structure is curved or beveled.

17 . A memory system device, comprising:

a controller coupled to a semiconductor memory device to control data storage operations on the semiconductor memory device; and

the semiconductor memory device comprising:

a memory stack of gate layers and insulating layers, the gate layers and the insulating layers being stacked alternatingly and being formed into stair steps in a staircase region;

a first landing pad on a first gate layer of a first stair step, the first gate layer being a top gate layer of the first stair step; and

a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step, the second gate layer being a top gate layer of the second stair step and being stacked on the first gate layer in the memory stack, the first sidewall isolation structure isolating the second gate layer from the first landing pad, wherein

the first sidewall isolation structure is in direct contact with the second gate layer and the first landing pad,

the first landing pad has a recessed area having a sidewall structure that is in direct contact with the first sidewall isolation structure, and

the recessed area is filled with a dielectric material.

18 . The memory system device of claim 17 , further comprising:

a second landing pad on the second gate layer of the second stair step, a sidewall of the second landing pad being covered by a different isolation layer from the first sidewall isolation structure.

19 . The memory system device of claim 18 , wherein the different isolation layer is a contact isolation layer in the staircase region, the contact isolation layer covers the first landing pad and the second landing pad.

20 . The memory system device of claim 19 , further comprising:

a first contact structure extending through the contact isolation layer and being connected with the first gate layer of the first stair step; and

a second contact structure extending through the contact isolation layer and being connected with the second gate layer of the second stair step.